Zilog Z80230 - Manual (Page 235)

SCC/ESCC
User Manual
UM010903-0515 Application Notes
228
SCC I/O Read/Write Cycle
Assume that the Z180 MPU’s /IOC bit in the OMCR (Operation Mode Control Register) clears to
0 (this condition is a Z80 ® compatible timing mode for /IORQ and /RD). The following are sev-
eral design points to consider (also see Table on page 214).
I/O Read Cycle
Parameters 8 and 9 explains that Address is stable 20 ns before the falling edge of /RD and until /
RD goes inactive.
Parameters 19 and 20 explains that /CE is stable at the falling edge of /RD and until /RD goes
inactive.
Parameter 22 explains the /RD pulse width is wider than 125 ns.
Parameters 25 and 27 explains that Read data is available on the data bus 120 ns later than the fall-
ing edge of /RD and 180 ns from a stable Address.
I/O Write Cycle
Parameters 6 and 7 explains that Address is stable 50 ns before the falling edge of /WR and is sta-
ble until /WR goes inactive.
Parameters 16 and 17 explains that /CE is stable at the falling edge of /WR and is stable until /W
goes inactive.
Parameter 28 explains /WR pulse width is wider than 125 ns.
Parameters 28 and 29 explains that Write data is on the data bus 10 ns before the falling edge of /
WR. It is stable until the rising edge of /WR.
Table and Table list the worst case SCC parameters calculating Z180 parameters at 10 MHz.
20 ThCE(RD) /CE to /RD High Hold 0 ns
22 TwRDI /RD Low Width 125 ns
25 TdRDf(DR) /RD Low to Read Data Valid 120 ns
27 TdA(DR) Address to Read Data Valid 180 ns
28 TwWRI /WR Low Width 125 ns
29 TsDW(WR) Write Data to /WR Low Setup 10 ns
30 TdWR(W) Write Data to /WR High Hold 0 ns
10 MHz SCC Timing Parameters for I/O Read/Write Cycle (Worst Case)
No Symbol Parameter Min Max Units