Zilog Z80230 - Manual (Page 158)

SCC/ESCC
User Manual
UM010903-0515 Register Descriptions
151
1X Mode (00).
The clock rate and data rate are the same. In External Sync mode, this bit combina-
tion specifies that only the /SYNC pin is used to achieve character synchronization.
16X Mode (01).
The clock rate is 16 times the data rate. In External Sync mode, this bit combina-
tion specifies that only the /SYNC pin is used to achieve character synchronization.
32X Mode (10).
The clock rate is 32 times the data rate. In External Sync mode, this bit combina-
tion specifies that either the /SYNC pin or a match with the character stored in WR7 will signal
character synchronization. The sync character can be either six or eight bits long as specified by
the 6-bit/8-bit sync bit in WR10.
64X Mode (11).
The clock rate is 64 times the data rate. With this bit combination in External
Sync mode, both the receiver and transmitter are placed in SDLC mode. The only variation from
normal SDLC operation is that the /SYNC pin is used to start or stop the reception of a frame by
forcing the receiver to act as though a flag had been received.
Bits 5 and 4: SYNC Mode selection bits 1 and 0
These two bits select the various options for
character synchronization. They are ignored unless synchronous modes are selected in the stop
bits field of this register.
Monosync Mode (00).
In this mode, the receiver achieves character synchronization by matching
the character stored in WR7 with an identical character in the received data stream. The transmit-
ter uses the character stored in WR6 as a time fill. The sync character is either six or eight bits,
depending on the state of the 6-bit/8-bit sync bit in WR10. If the Sync Character Load Inhibit bit is
set, the receiver strips the contents of WR6 from the data stream if received within character
boundaries.
Bisync Mode (01).
The concatenation of WR7 with WR6 is used for receiver synchronization and
as a time fill by the transmitter. The sync character is 12 or 16 bits in the receiver, depending on
the state of the 6-bit/8-bit sync bit in WR10. The transmitted character is always 16 bits.
SDLC Mode (10).
In this mode, SDLC is selected and requires a Flag (01111110) to be written to
WR7. The receiver address field is written to WR6. The SDLC CRC polynomial is also selected
(WR5) in SDLC mode.
External Sync Mode (11).
In this mode, the SCC expects external logic to signal character syn-
chronization via the /SYNC pin. If the crystal oscillator option is selected (in WR11), the internal /
SYNC signal is forced to 0. In this mode, the transmitter is in Monosync mode using the contents
of WR6 as the time fill with the sync character length specified by the 6-bit/8-bit Sync bit in
WR10.
Bits 3 and 2: Stop Bits selection, bits 1 and 0
These bits determine the number of stop bits added
to each asynchronous character that is transmitted. The receiver always checks for one stop bit in
Asynchronous mode. A special mode specifies that a Synchronous mode is to be selected. D2 is
always set to 1 by a channel or hardware reset to ensure that the /SYNC pin is in a known state
after a reset.
Synchronous Modes Enable (00).
This bit combination selects one of the synchronous modes
specified by bits D4, D5, D6, and D7 of this register and forces the 1X Clock mode internally.