Zilog Z80230 User Manual
Page 139
SCC/ESCC
User Manual
UM010903-0515
Data Communication Modes
132
the CPU writes its data bytes to the SCC, just as in normal SDLC frame transmission. When the
frame is complete and CRC has been sent, the SCC closes with a flag and reverts to One-Bit-
Delay mode. The last zero of the flag, along with the marking line echoed from the RxD pin, form
an EOP for secondary stations further down the loop.
While the SCC is actually transmitting a message, the loop-sending bit in R10 is set to indicate
this.
If the Go-Active-On-Poll bit is not set at the time the EOP passes by, the SCC cannot send a mes-
sage until a flag (terminating the current polling sequence) and another EOP are received.
If SDLC loop is deselected, the SCC is designed to exit from the loop gracefully. When the SDLC
Loop mode is deselected by writing to WR10, the SCC waits until the next polling cycle to
remove the one-bit time delay.
If a polling cycle is in progress at the time the command is written, the SCC finishes sending any
message that it is transmitting, ends with an EOP, and disconnects TxD from RxD. If no message
was in progress, the SCC immediately disconnects TxD from RxD.
Once the SCC is not sending on the loop, exiting from the loop is accomplished by setting the
Loop Mode bit in WR10 to 0, and at the same time writing the Abort/Flag on Underrun and Mark/
Flag idle bits with the desired values. The SCC will revert to normal SDLC operation as soon as
an EOP is received, or immediately if the receiver is already in Hunt mode because of the receipt
of an EOP.
To ensure proper loop operation after the SCC goes off the loop, and until the external relays take
the SCC completely out of the loop, the SCC should be programmed for Mark idle instead of Flag
idle. When the SCC goes off the loop, the On-Loop bit is reset.
With NRZI encoding, removing the stations from the loop (removing the one-bit time delay)
may cause problems further down the loop because of extraneous transitions on the line.
The SCC avoids this problem by making transparent adjustments at the end of each frame it
sends in response to an EOP. A response frame from the SCC is terminated by a flag and
EOP. Normally, the flag and the EOP share a zero, but if such sharing would cause the RxD
and TxD pins to be of opposite polarity after the EOP, the SCC adds another zero between
the flag and the EOP. This causes an extra line transition so that RxD and TxD are identi-
cal after the EOP is sent. This extra zero is completely transparent because it only means
that the flag and the EOP no longer share a zero. All that a proper loop exit needs, there-
fore, is the removal of the one-bit delay.
The SCC allows the user the option of using NRZI in SDLC Loop mode by programming WR10
appropriately. With NRZI encoding, the outputs of secondary stations in the loop are inverted from
their inputs because of messages that they have transmitted.
Subsections
discuss the SDLC Loop
Mode in Receive and Transmit.
Note: