Zilog Z80230 User Manual
Page 152
SCC/ESCC
User Manual
UM010903-0515
Register Descriptions
145
When programmed to 1, this bit allows the Wait/Request function to follow the state of the receive
buffer. Thus, depending on the state of bit 6, the /W//REQ pin is active or inactive in relation to the
empty or full state of the receive buffer.
The request function occurs only when the SCC is not selected; e.g., if the internal request
becomes active while the SCC is in the middle of a read or write cycle, the external request does
not become active until the cycle is complete. An active request output causes a DMA controller
to initiate a read or write operation. If the request on Transmit mode is selected in either SDLC or
Synchronous Mode, the Request pin is pulsed Low for one PCLK cycle at the end of CRC trans-
mission to allow the immediate transmission of another block of data.
In the Wait On Receive mode, the /WAIT pin is active if the CPU attempts to read SCC data that
has not yet been received. In the Wait On Transmit mode, the /WAIT pin is active if the CPU
attempts to write data when the transmit buffer is still full. Both situations occur frequently when
block transfer instructions are used.
Bits 4 and 3: Receive Interrupt Modes Receive Interrupts Disabled (00).
This mode prevents
the receiver from requesting an interrupt. It is normally used in a polled environment where either
the status bits in RR0 or the modified vector in RR2 (Channel B) are monitored to initiate a service
routine. Although the receiver interrupts are disabled, a special condition can still provide a unique
vector status in RR2.
Receive Interrupt on First Character or Special Condition (01).
The receiver requests an inter-
rupt in this mode on the first available character (or stored FIFO character) or on a special condi-
tion. Sync characters, stripped from the message stream, do not cause interrupts.
1
0
0
1
WR9A (RR13A)
(RR13A)
(WR3A)
1
0
1
0
WR10A RR10A
RR10A
RR10A
1
0
1
1
WR11A (RR15A)
(RR15A)
(WR10A)
1
1
0
0
WR12A RR12A
RR12A
RR12A
1
1
0
1
WR13A RR13A
RR13A
RR13A
1
1
1
0
WR14A RR14A
RR14A
(WR7’A)
1
1
1
1
WR15A RR15A
RR15A
RR15A
Notes
1. WR15 bit D2 enables status FIFO function. (Not available on NMOS).
2. WR7' bit D6 enables extend read function. (Only on ESCC and 85C30).
3. * Includes 85C30 and 85230/L with WR15 D2=0.
Z85X30 Register Map (Continued)
READ 8530
85C30/85230W
85C30/230*
85C30/230 R15 D2=1
A//B PNT2 PNT1 PNT0 WRITE WR15 D2 = 0 WR15 D2=1 WR7' D6=1