Zilog Z80230 - Manual (Page 55)

SCC/ESCC
User Manual
UM010903-0515 Interfacing the SCC/ESCC
48
the receive data FIFO so that the service routine must read the status in RR1 before reading the
data.
At moderate to high data rates where the interrupt overhead is significant, time can usually be
saved by checking for another character before exiting the service routine. This technique elimi-
nates the interrupt acknowledge and the status processing, saving time, but care must be exercised
because this receive character must be checked for special receive conditions before it is removed
from the SCC.
Receive Interrupt on Special Conditions
This mode is designed for use when a DMA transfers all receive characters between memory and
the SCC. In this mode, only receive characters with special conditions will cause the receive IP to
be set. All other characters are assumed to be transferred via DMA. No special initialization
sequence is needed in this mode. Usually, the DMA is initialized and enabled, then this mode is
selected in the SCC. A special receive condition interrupt may occur at any time after this mode is
selected, but the logic guarantees that the interrupt will not occur until after the character with the
special condition has been read from the SCC. The special condition locks the FIFO so that the
status is valid when read in the interrupt service routine, and it guarantees that the DMA will not
transfer any characters until the special condition has been serviced.
In the service routine, the processor should read RR1 to obtain the status and unlock the FIFO by
issuing an Error Reset command. DMA transfer of the receive characters then resumes. Figure on
page 49 displays the special conditions interrupt service routine.
1. On the CMOS and ESCC, if the SDLC Frame Status FIFO is being used, see SDLC
Frame Status FIFO
on page 126 on the FIFO anti-lock feature.
2. Special Receive Condition interrupts are generated after the character is read from
the FIFO, not when the special condition is first detected. This is done so that when
using receive interrupt on first or Special Condition or Special Condition Only, data is
directly read out of the data FIFO without checking the status first. If a special condi-
tion interrupted the CPU when first detected, it would be necessary to read RR1
before each byte in the FIFO to determine which byte had the special condition.
Therefore, by not generating the interrupt until after the byte has been read and then
locking the FIFO, only one status read is necessary. A DMA can be used to do all data
transfers (otherwise, it would be necessary to disable the DMA to allow the CPU to
read the status on each byte). Consequently, since the special condition locks the
FIFO to preserve the status, it is necessary to issue the Error Reset command to
Notes: