Zilog Z80230 - Manual (Page 57)

SCC/ESCC
User Manual
UM010903-0515 Interfacing the SCC/ESCC
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empty. Transmit interrupts should also be disabled in the case of DMA transfer of the transmitted
data.
Because the depth of the transmitter buffer is different between the NMOS/CMOS version of the
SCC and ESCC, generation of the transmit interrupt is slightly different. The following subsec-
tions describe transmit interrupts.
For all interrupt sources, the Master Interrupt Enable (MIE) bit, WR9 bit D3, must be set
for the device to generate a transmit interrupt.
Transmit Interrupts and Transmit Buffer Empty Bit on the NMOS/CMOS
The NMOS/CMOS version of the SCC only has a one byte deep transmit buffer. The status of the
transmit buffer can be determined through TBE bit in RR0, bit D2, which shows whether the
transmit buffer is empty or not. After a hardware reset (including a hardware reset by software), or
a channel reset, this bit is set to 1.
While transmit interrupts are enabled, the NMOS/CMOS version sets the Transmit Interrupt Pend-
ing (TxIP) bit whenever the transmit buffer becomes empty. This means that the transmit buffer
must be full before the TxIP can be set. Thus, when transmit interrupts are first enabled, the TxIP
will not be set until after the first character is written to the NMOS/CMOS. In synchronous modes,
one other condition can cause the TxIP to be set. This occurs at the end of a transmission after the
CRC is sent. When the last bit of the CRC has cleared the Transmit Shift Register and the flag or
sync character is loaded into the Transmit Shift Register, the NMOS/CMOS version sets the TxIP
and TBE bit. Data for a second frame or block transmission may be written at this time.
The TxIP is reset either by writing data to the transmit buffer or by issuing the Reset Tx Int com-
mand in WR0. Ordinarily, the response to a transmit interrupt is to write more data to the device;
however, the Reset Tx Int command should be issued in lieu of data at the end of a frame or a
block of data where the CRC is to be sent next.
A transmit interrupt may indicate that the packet has terminated illegally, with the CRC
byte(s) overwritten by the data. If the transmit interrupt occurs after the first CRC byte is
loaded into the Transmit Shift Register, but before the last bit of the second CRC byte has
cleared the Transmit Shift Register, then data was written while the CRC was being sent.
Transmit Interrupt and Transmit Buffer Empty bit on the ESCC
The ESCC has a 4-byte deep Transmit FIFO, while the NMOS/CMOS SCC is just 1-byte deep.
For this reason, the generation of transmit interrupts is slightly different from that of the NMOS/
CMOS SCC version. The ESCC has two modes of transmit interrupt generation, which are pro-
grammed by bit D5 of WR7'. One transmit mode generates interrupts when the entry location (the
location the CPU writes data) of the Transmit FIFO is empty. This allows the ESCC response to be
tailored to system requirements for the frequency of interrupts and the interrupt response time. On
the other hand, the Transmit Buffer Empty (TBE) bit on the ESCC will respond the same way in
each mode, in which the bit will become set when the entry location of the Transmit FIFO is
empty. The TBE bit is not directly related to the transmit interrupt status nor the state of WR7' bit
D5.
Note:
Note: