Zilog Z80230 - Manual (Page 233)

SCC/ESCC
User Manual
UM010903-0515 Application Notes
226
Z80 Interrupt Daisy-Chain Operation
In the Z80 peripherals, both IP and IUS bits control the IEO line and the lower portion of the daisy
chain. When a peripheral’s IP bit sets, the IEO line goes Low. This is true regardless of the state of
the IEI line. Additionally, if the peripheral’s IUS bit clears and its IEI line is High, the /INT line
goes Low.
The Z80 peripherals sample for both /M1 and /IORQ active (and /RD inactive) to identify an Inter-
rupt Acknowledge cycle. When /M1 goes active and /RD is inactive, the peripheral detects an
Interrupt Acknowledge cycle and allows its interrupt daisy chain to settle. When the /IORQ line
goes active with /M1 active, the highest priority interrupting peripheral places its interrupt vector
onto the data bus. The IUS bit also sets to show that the peripheral is now under service. As long
as the IUS bit sets, the IEO line remains Low. This inhibits any lower priority devices from
requesting an interrupt.
When the Z180 CPU executes the RETI instruction, the peripherals check the data bus and the
highest priority device under service resets its IUS bit.
SCC Interrupt Daisy-Chain Operation
In the SCC, the IUS bit normally controls the state of the IEO line. The IP bit affects the daisy
chain only during an Interrupt Acknowledge cycle. Since the IP bit is normally not part of the SCC
interrupt daisy chain, there is no need to decode the RETI instruction. To allow for control over the
daisy chain, the SCC has a Disable Lower Chain (DLC) software command that pulls IEO Low.
This selectively deactivates parts of the daisy chain regardless of the interrupt status. Table lists
the truth table for the SCC interrupt daisy chain control signals during certain cycles. Table on
page 239 lists SCC Test Program for the Interrupt.
SCC Daisy Chain Signal Truth Table
During Idle State During INTACK Cycle
IEI IP IUS IEO IEI IP IUS IEO
0 X X 0 0 X X 0
1 X 0 1 1 1 X 0
1 X 1 0 1 X 1 0
1 0 0 1