Zilog Z80230 - Manual (Page 48)

SCC/ESCC
User Manual
UM010903-0515 Interfacing the SCC/ESCC
41
IUS bits can be set by either a hardware acknowledge cycle with the /INTACK pin or through soft-
ware if WR9 D5=1 and then reading RR2.
The IUS bits control the operation of internal and external daisy-chain interrupts. The internal
daisy chain links the six sources of interrupt in a fixed order, chaining the IUS bit of each source.
If an internal IUS bit is set, all lower priority interrupt requests are masked off; during an interrupt
acknowledge cycle the IP bits are also gated into the daisy chain. This ensures that the highest pri-
ority IP selected has its IUS bit set. At the end of an interrupt service routine, the processor must
issue a Reset Highest IUS command in WR0 to re-enable lower priority interrupts. This is the only
way, short of a software or hardware reset, that an IUS bit may be reset.
It is not necessary to issue the Reset Highest IUS command in the interrupt service rou-
tine, since the IUS bits can only be set by an interrupt acknowledge if no hardware
acknowledge or software acknowledge cycle (not with NMOS) is executed. The only
exception is when the SDLC Frame Status FIFO (not with NMOS) is enabled and
“receive interrupt on special condition only” is used. See
SDLC Frame Status FIFO
on
page 126 for more details on this mode.
Disable Lower Chain Bit
The Disable Lower Chain (DLC) bit in WR9 (D2) is used to disable all peripherals in a lower posi-
tion on the external daisy chain. If WR9 D2=1, the IEO pin is driven Low and prevents lower pri-
ority devices from generating an interrupt request. Note that the IUS bit, when set, will have the
same effect, but is not controllable through software.
Daisy-Chain Resolution
The six sources of interrupt in the SCC are prioritized in a fixed order via a daisy chain; provision
is made, via the IEI and IEO pins, for use of an external daisy chain as well. All Channel A inter-
rupts are higher priority than any Channel B interrupts, with the receiver, transmitter, and Exter-
nal/Status interrupts prioritized in that order within each channel. The SCC requests an interrupt
by pulling the /INT pin Low from its open-drain state. This is controlled by the IP bits and the IEI
input, among other things. A flowchart of the interrupt sequence for the SCC is displayed in
Figure on page 43.
The internal daisy chain links the six sources of interrupt in a fixed order, chaining the IUS bits for
each source. While an IUS bit is set, all lower priority interrupt requests are masked off, thus pre-
venting lower priority interrupts, but still allowing higher priority interrupts to occur. Also, during
an interrupt acknowledge cycle the IP bits are gated into the daisy chain. This insures that the
highest priority IP is selected to set IUS. The internal daisy chain may be controlled by the MIE bit
in WR9. This bit, when reset, has the same effect as pulling the IEI pin Low, thus disabling all
interrupt requests.
External Daisy-Chain Operations
The SCC generates an interrupt request by pulling /INT Low, but only if such interrupt requests
are enabled (IE is 1, MIE is 1) and all of the following conditions occur:
Note: