Zilog Z80230 - Manual (Page 153)

SCC/ESCC
User Manual
UM010903-0515 Register Descriptions
146
Special receive conditions are: receiver overrun, framing error, end of frame, or parity error (if
selected). If a special receive condition occurs, the data containing the error is stored in the
Receive FIFO until an Error Reset command is issued by the CPU.
This mode is usually selected when a Block Transfer mode is used. In this interrupt mode, a pend-
ing special receive condition remains set until either an error Reset command, a channel or hard-
ware reset, or until receive interrupts are disabled.
The Receive Interrupt on First Character or Special Condition mode can be re-enabled by the
Enable Rx Interrupt on Next Character command in WR0.
ESCC:
See the description of WR7' on how this function can be changed.
Interrupt on All Receive Characters or Special Condition (10).
This mode allows an interrupt
for every character received (or character in the Receive FIFO) and provides a unique vector when
a special condition exists. The Receiver Overrun bit and the Parity Error bit in RR1 are two special
conditions that are latched. These two bits are reset by the Error Reset command. Receiver over-
run is always a special receive condition, and parity can be programmed to be a special condition.
Data characters with special receive conditions are not held in the Receive FIFO in the Interrupt
On All Receive Characters or Special Conditions Mode as they are in the other receive interrupt
modes.
Receive Interrupt on Special Condition (11).
This mode allows the receiver to interrupt only on
characters with a special receive condition. When an interrupt occurs, the data containing the error
is held in the Receive FIFO until an Error Reset command is issued. When using this mode in con-
junction with a DMA, the DMA is initialized and enabled before any characters have been
received by the ESCC. This eliminates the time-critical section of code required in the Receive
Interrupt on First Character or Special Condition mode. Hence, all data can be transferred via the
DMA so that the CPU need not handle the first received character as a special case. In SDLC
mode, if the SDLC Frame Status FIFO is enabled and an EOF is received, an interrupt with vector
for receive data available is generated and the Receive FIFO is not locked.
Bit 2: Parity Is Special Condition
If this bit is set to 1, any received characters with parity not matching the sense programmed in
WR4 give rise to a Special Receive Condition. If parity is disabled (WR4), this bit is ignored. A
special condition modifies the status of the interrupt vector stored in WR2. During an interrupt
acknowledge cycle, this vector can be placed on the data bus.