Zilog Z80230 - Manual (Page 166)

SCC/ESCC
User Manual
UM010903-0515 Register Descriptions
159
depending on the speed grade of the device). When this bit is reset to 0, the deactivation time for
the /DTR//REQ pin is 4TcPc.
Bit 3: Force TxD High.
In the SDLC mode of operation with the NRZI encoding mode, there is an option to force TxD
High. If bit D0 of WR15 is set to 1, bit D3 of WR7' can be used to set TxD pin High.
Note that the operation of this bit is independent of the Tx Enable bit in WR5 is used to control
transmission activities, whereas bit D3 of WR7' acts as a pseudo transmitter may actually be mark
or flag idling. Care must be exercised when setting this bit because any character being transmitted
at the time that bit is set is “chopped off”; data written to the Transmit Buffer while this bit is set is
lost.
Bit 2: Auto /RTS pin Deactivation
This bit controls the timing of the deassertion of the /RTS pin. If this device is programmed for
SDLC mode and Flag-On-Underrun (WR10 D2=0), this bit is set and the RTS bit is reset. The /
RTS is deasserted automatically at the last bit of the closing flag, triggered by the rising edge of
the TxC. If this bit is reset to 0, the /RTS pin follows the state programmed in WR5 bit D1.
Bit 1: Automatic Tx Underrun/EOM Latch Reset
If this bit is set, this version automatically resets the Tx Underrun/EOM latch and presets the trans-
mit CRC generator to its programmed preset state (the values set in WR5 D2 & WR10 D7). This
removes the requirement to issue the Reset Tx Underrun/EOM latch command. Also, this feature
enables a write transmit data before enabling the transmitter.
Bit 0: Automatic SDLC Opening Flag Transmission.
If this bit is set, the device automatically transmits an SDLC opening flag before transmitting data.
This removes the requirement to reset the mark idle bit (WR10, bit D3) before writing data to the
transmitter, or having to enable the transmitter before writing data to the Transmit buffer. Also,
this feature enables a write transmit data before enabling the transmitter.
Write Register 8 (Transmit Buffer)
WR8 is the transmit buffer register.
Write Register 9 (Master Interrupt Control)
WR9 is the Master Interrupt Control register and contains the Reset command bits. Only one WR9
exists in the SCC and is accessed from either channel. The Interrupt control bits are programmed