Zilog Z80230 - Manual (Page 65)

SCC/ESCC
User Manual
UM010903-0515 Interfacing the SCC/ESCC
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twice to detect changes that otherwise may be missed. The contents of RR0 are latched on the fall-
ing edge of /RD and are updated after the rising edge of /RD.
The operation of the individual enable bits in WR15 for each of the six sources of External/Status
interrupts is identical, but subtle differences exist in the operation of each source of interrupt. The
six sources are Break/Abort, Underrun/EOM, CTS, DCD, Sync/Hunt and Zero Count. The Break/
Abort, Underrun/EOM, and Zero Count conditions are internal to the SCC, while Sync/Hunt may
be internal or external, and CTS and DCD are purely external signals. In the following discus-
sions, each source is assumed to be enabled so that the latches are present and the External/Status
interrupts are enabled as a whole. Recall that the External/Status IP is set while the latches are
closed and that the state of the signal is reflected immediately in RR0 if the latches are not present.
Break/Abort
The Break/Abort status is used in asynchronous and SDLC modes, but is always 0 in synchronous
modes other than SDLC. In asynchronous modes, this bit is set when a break sequence (null char-
acter plus framing error) is detected in the receive data stream, and remains set as long as 0s con-
tinue to be received. This bit is reset when a 1 is received. A single null character is left in the
Receive FIFO each time that the break condition is terminated. This character should be read and
discarded.
In SDLC mode, this bit is set by the detection of an abort sequence which is seven or more contig-
uous 1s in the receive data stream. The bit is reset when a 0 is received. A received abort forces the
receiver into Hunt, which is also an external/status condition. Though these two bits change state
at roughly the same time, one or two External/Status Interrupts may be generated as a result. The
Break/Abort bit is unique in that both transitions are guaranteed to cause the latches to close, even
if another External/Status interrupt is pending at the time these transitions occur. This guarantees
that a break or abort will be caught. This bit is undetermined after reset.
Transmit Underrun/EOM
The Transmit Underrun/EOM bit is used in synchronous modes to control the transmission of the
CRC. This bit is reset by issuing the Reset Transmit Underrun/EOM command in WR0. However,
this transition does not cause the latches to close; this occurs only when the bit is set. To inform the
processor of this fact, the SCC sets this bit when the CRC is loaded into the Transmit Shift Regis-
ter. This bit is also set if the processor issues the Send Abort command in WR0. This bit is always
set in Asynchronous mode.
ESCC:
The ESCC has been modified so that in SDLC mode this interrupt indicates when more data
can be written to the Transmit FIFO. When this interrupt is used in this way, the Automatic
SDLC Flag Transmission feature must be enabled (WR7' D0=1). On the ESCC, the Transmit
Underrun/EOM interrupt can be used to signal when data for a subsequent frame can be writ-
ten to the Transmit FIFO which more easily supports the transmission of back to back frames.