Zilog Z80230 - Manual (Page 259)

SCC/ESCC
User Manual
UM010903-0515 Application Notes
252
The ISCC and IUSC handle their own DMA transfers through the 80186’s HOLD/HLDA facility.
Either a Z16C33 MUSC or a Z16C30 USC can be installed in socket U5. If this is the case,
references to (M)USC in the following discussion may mean the USC in its entirety or just
channel A. Which one should be clear from the context.
The inputs and outputs associated with the processor’s integrated counter/timer facility are
brought to the pin header labelled J26 so that they can be used in applications as listed in Table .
The 80186’s integrated interrupt controller is bypassed in favor of the Zilog ® interrupt daisy-chain
structure.
80186 DMA Jumper Connections
DMA Channel Function Install This Jumper
0 (E)SCC B Rx J23-1 to J23-2
0 MUSC Rx or USC A Rx J22-1 to J22-2
0 MUSC Tx or USC A Tx J22-4 to J22-2
0 USC B Rx J29-1 to J29-2
0 USC B Tx J29-4 to J29-2
1 ESSCC B Tx J24-1 to J24-3
1 (E)SCC B Tx w/early release J24-1 to J24-2
1 MUSC Rx or USC A Rx J22-1 to J22-3
1 MUSC Tx or USC A Tx J22-4 to J22-1
1 USC B Rx J29-1 to J29-3
1 USC B Tx J29-4 to J29-3
Counter/Timer Signal Locations
J26 Pin Signal
1 Timer In 1
2 Timer Out 1
3 Timer In 0
4 Timer Out 0
5 N/C
6 Ground
Note: