Zilog Z80230 - Manual (Page 36)

SCC/ESCC
User Manual
UM010903-0515 Interfacing the SCC/ESCC
29
Z85X30 Write Cycle Timing
Z85X30 Interrupt Acknowledge Cycle Timing
The interrupt acknowledge cycle timing for the Z85X30 is displayed in Figure on page 29. The
state of /INTACK is latched by the rising edge of PCLK (AC Spec #10). While /INTACK is Low,
the state of A//B, /CE, D//C, and /WR are ignored.
Z85X30 Interrupt Acknowledge Cycle Timing
A//B, D//C
/INTACK
/CE
/WR
D7-D0
Address Valid
Data Valid
See Note
Note: Dotted line is ESCC only.
/INTACK
/RD
D7-D0 Vector