Zilog Z80230 - Manual (Page 98)

SCC/ESCC
User Manual
UM010903-0515 Data Communication Modes
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character programmed in WR7 and the character assembled in the Receive Sync register to estab-
lish synchronization.
Synchronization is achieved differently in the Bisync mode. Incoming data is shifted to the
Receive Shift register while the next eight bits of the message are assembled in the Receive Sync
register. If these two characters match the programmed characters in WR6 and WR7, synchroniza-
tion is established. Incoming data can then bypass the Receive Sync register and enter the 3-bit
delay directly.
The SDLC mode of operation uses the Receive Sync register to monitor the receive data stream
and to perform zero deletion when necessary; i.e., when five continuous 1s are received, the sixth
bit is inspected and deleted from the data stream if it is 0. The seventh bit is inspected only if the
sixth bit equals one. If the seventh bit is 0, a flag sequence has been received and the receiver is
synchronized to that flag. If the seventh bit is a 1, an abort or an EOP (End Of Poll) is recognized,
depending upon the selection of either the normal SDLC mode or SDLC Loop mode.
The insertion and deletion of the zero in the SDLC data stream is transparent to the user, as
it is done after the data is written to the Transmit FIFO and before data is read from the
Receive FIFO. This feature of the SDLC/HDLC protocol is to prevent the inadvertent send-
ing of an ABORT sequence as part of the data stream. It is also valuable to applications
using encoded data to insure a sufficient number of edges on the line to keep a DPLL syn-
chronized on a receive data stream.
The same path is taken by incoming data for both SDLC and SDLC Loop modes. The reformatted
data enters the 3-bit delay and is transferred to the Receive Shift register. The SDLC receive oper-
ation begins in the hunt phase by attempting to match the assembled character in the Receive Shift
Register with the flag pattern in WR7. When the flag character is recognized, subsequent data is
routed through the same path, regardless of character length.
Either the CRC-16 or CRC-SDLC (cyclic redundancy check or CRC) polynomial can be used for
both Monosync and Bisync modes, but only the CRC-SDLC polynomial is used for SDLC opera-
tion. The data path taken for each mode is also different. Bisync protocol is a byte-oriented opera-
tion that requires the CPU to decide whether or not a data character is to be included in CRC
calculation. An 8bit delay in all Synchronous modes except SDLC is allowed for this process. In
SDLC mode, all bytes are included in the CRC calculation.
Note: