Zilog Z80230 - Manual (Page 37)

SCC/ESCC
User Manual
UM010903-0515 Interfacing the SCC/ESCC
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Between the time /INTACK is first sampled Low and the time /RD falls, the internal and external
IEI/IEO daisy chain settles (AC parameter #38 TdIAI(RD) Note 5). A system with no external
daisy chain must provide the time specified in AC Spec #38 to settle the interrupt daisy chain pri-
ority internal to the SCC. Systems using the external IEI/IEO daisy chain should refer to Note 5
referenced in the Z85X30 Read/Write and Interrupt Acknowledge Timing for the time required to
settle the daisy chain.
/INTACK is sampled on the rising edge of PCLK. If it does not meet the setup time to the
first rising edge of PCLK of the interrupt acknowledge cycle, it is latched on the next rising
edge of PCLK. Therefore, if /INTACK is asynchronous to PCLK, it may be necessary to add
a PCLK cycle to the calculation for /INTACK to /RD delay time.
If there is an interrupt pending in the Z85X30, and IEI is High when /RD falls, the interrupt
acknowledge cycle was intended for the Z85X30. In this case, the Z85X30 sets the appropriate
Interrupt-Under-Service latch, and places an interrupt vector on D7-D0.
If the falling edge of /RD sets an IUS bit in the Z85X30, the /INT pin goes inactive in response to
the falling edge. Note that there should be only one /RD per acknowledge cycle.
1. The IP bits in the Z85X30 are updated by PCLK. However, when the register pointer is
pointing to RR2 and RR3, the IP bits are prevented from changing. This prevents data
changing during a read, but will delay interrupt requests if the pointers are left point-
ing at these registers.
2. The SCC should only receive one INTACK signal per acknowledge cycle. Therefore, if
the CPU generates more than one (as is common for the 80X86 family), an external
circuit should be used to convert this into a single pulse or does not use Interrupt
Acknowledge.
Z85X30 Register Access
The registers in the Z85X30 are accessed in a two step process, using a Register Pointer to perform
the addressing. To access a particular register, the pointer bits are set by writing to WR0. The
pointer bits may be written in either channel because only one set exists in the Z85X30. After the
pointer bits are set, the next read or write cycle of the Z85X30 having D//C Low will access the
desired register. At the conclusion of this read or write cycle the pointer bits are reset to 0s, so that
the next control write is to the pointers in WR0.
A read to RR8 (the receive data FIFO) or a write to WR8 (the transmit data FIFO) is either done in
this fashion or by accessing the Z85X30 having D//C pin High. A read or write with D//C High
accesses the data registers directly, and independently of the state of the pointer bits. This allows
single-cycle access to the data registers and does not disturb the pointer bits.
The fact that the pointer bits are reset to 0, unless explicitly set otherwise, means that WR0 and
RR0 may also be accessed in a single cycle. That is, it is not necessary to write the pointer bits
with 0 before accessing WR0 or RR0.
Note:
Notes: