Zilog Z80230 - Manual (Page 265)

SCC/ESCC
User Manual
UM010903-0515 Application Notes
258
as the speeds possible with a DMA approach. To use the W/REQB output as a Receive DMA
Request, jumper J23-J1 to J23-J2 and leave J23-J3 open.
Jumper block J24 determine’s how Channel B’s DTR/REQB output is used. To use this output for
the Data Terminal Ready function, jumper J24-J3 to J24-J4 and leave J24-J1 and J24-J2 open. To
use this output directly as a Transmit DMA Request (using the (E)SCC’s early release capability),
jumper J24-J1 to J24-J3 and leave J24-J2 and J24-J4 open. To drive the Transmit DMA Request
with a clipped version of the signal that is forced High earlier than a standard SCC drives it High,
jumper J24-J1 to J24-J2 and leave J24-J3 and J24-J4 open.
The
SCC EPLSD
handles the (E)SCC’s signaling requirements. The EPLD configures the (E)SCC
socket’s Pins 35 and 36 for either a multiplexed or non-multiplexed part, based on whether J20 is
jumpered to connect the 80186 ALE signal to one of the input pins. If the device detects high-
going pulses on this input, it drives the corresponding low-going Address Strobe pulses onto
(E)SCC
Pin 36.
If the SCC EPLD’s Pin 9 stays at ground, the part drives Read strobes onto Pin 36 and drives
delayed Write strobes onto Pin 35, for a non-multiplexed 85x30 device.
While the ESCC’s relaxed timing capability allows the 80186’s WR output to be connected
directly to the WR input of a non-multiplexed ESCC, the SCC EPLD delays start of the SCC’s
write cycle until write data is valid, even though this is not 
necessary for an ESCC.
The ESCC EPLD also generates the clipped DMA-request mentioned in connection with J24, and
logically ORs Reset onto Pins 35 and 36. The device also tracks the two IACK cycles provided by
the 80186 for each Interrupt Acknowledge cycle. For a multiplexed address/data port, it drives the
address strobe only on the first cycle and provides the RD or DS pulse needed by the (E)SCC only
on the second cycle. The
DMA EPLD
provides the INTACK signal needed by the (E)SCC.
The (E)SCC is only accessible at even addresses. For a non-multiplexed part (85x30), the four reg-
ister locations (see Table ) are repeated throughout the even addresses from (PBA) the (PBA)
+126.
For a multiplexed part (80x30), the Select Shift Left command (
D1-D0=11
) must be written to
Channel B’s WR0 before any other registers are accessed.
Register Locations
(PBA), (PBA)+8....(PBA)+120 Channel B Command/
Status Register
(PBA)+2, +10.......(PBA)+122 Channel B Data
Register
(PBA)+4, +12.......(PBA)+124 Channel A Command/
Status Register
(PBA)+6, +14.......(PBA)+126 Channel A Data
Register