Zilog Z80230 - Manual (Page 14)

SCC/ESCC
User Manual
UM010903-0515 General Description
7
Pin Descriptions
The SCC pins are divided into seven functional groups: Address/Data, Bus Timing and Reset,
Device Control, Interrupt, Serial Data (both channels), Peripheral Control (both channels), and
Clocks (both channels). Figure on page 8 and Figure on page 9 display the pins in each functional
group for both Z80X30 and Z85X30. Notice the pin functions unique to each bus interface version
in the Address/Data group, Bus Timing and Reset group, and Control groups.
The Address/Data group consists of the bidirectional lines used to transfer data between the CPU
and the SCC (Addresses in the Z80X30 are latched by /AS). The direction of these lines depends
on whether the operation is a Read or Write.
The timing and control groups designate the type of transaction to occur and when it will occur.
The interrupt group provides inputs and outputs to conform to the Z-Bus ® specifications for han-
dling and prioritizing interrupts. The remaining groups are divided into channel A and channel B
groups for serial data (transmit or receive), peripheral control (such as DMA or modem), and the
input and output lines for the receive and transmit clocks.