Zilog Z80230 - Manual (Page 104)

SCC/ESCC
User Manual
UM010903-0515 Data Communication Modes
97
The SCC may be programmed to accept a receive clock that is one, sixteen, thirty-two, or sixty-
four times the data rate. This is selected by bits D7 and D6 in WR4. The 1X mode is used when bit
synchronization external to the received clock is present (i.e., the clock recovery circuit, or active
receive clock from the sender side). The 1X mode is the only mode in which a data encoding
method other than NRZ may be used. The clock factor is common to the receiver and transmitter.
The break condition is continuous 0s, as opposed to the usual continuous ones during an idle con-
dition. The SCC recognizes the Break condition upon seeing a null character (all 0s) plus a fram-
ing error. Upon recognizing this sequence, the Break bit in RR0 is set and remains set until a 1 is
received. At this point, the break condition is no longer present. At the termination of a break, the
receive data FIFO contains a single null character, which should be read and discarded. The fram-
ing error bit will not be set for this character, but if odd parity has been selected, the Parity Error
bit is set.
Caution should be exercised if the receive data line contains a switch that is not debounced
to generate breaks. If this is the case, switch bounce may cause multiple breaks to be recog-
nized by the SCC, with additional characters assembled in the receive data FIFO and the
possibility of a receive overrun condition being latched.
The SCC provides up to three modem control signals associated with the receiver; /SYNC, /DTR//
REQ, and /DCD.
The /SYNC pin is a general purpose input whose state is reported in the Sync/Hunt bit in RR0. If
the crystal oscillator is enabled, this pin is not available and the Sync/Hunt bit is forced to 0. Oth-
erwise, the /SYNC pin may be used to carry the Ring Indicator signal.
The /DTR//REQ pin carries the inverted state of the DTR bit (D7) in WR5 unless this pin has been
programmed to carry a DMA request signal.
The /DCD pin is ordinarily a simple input to the DCD bit in RR0. However, if the Auto Enables
mode is selected by setting D5 of WR3 to 1, this pin becomes an enable for the receiver. That is, if
Auto Enables is on and the /DCD pin is High, the receiver is disabled; while the /DCD pin is low,
the receiver is enabled.
Received characters are assembled, checked for errors, and moved to the receive data FIFO (eight
bytes on ESCC, three bytes on NMOS/CMOS). The user can program the SCC to generate an
interrupt to the CPU or to request a data read from a DMA when data is received.
On the NMOS/CMOS version, it generates the Receive Character Available interrupt and DMA
Request on Receive (if enabled). The receive interrupt and DMA request is generated when there
is at least one character in the FIFO. The Rx Character Available (RCA) bit is set if there is at least
one byte available.
The ESCC generates the receive character available interrupt and DMA request on Receive (if
enabled) and is dependent on WR7' bit D3. If this bit is reset to 0 (this mode is comparable to the
NMOS/CMOS version), the receive interrupt and DMA request is generated when there is at least
one character in the FIFO. If WR7' bit D3 is set to 1, the receive interrupt and DMA request are
generated when there are four bytes available in the Receive FIFO. The RCA bit in RR0 follows
Note: