Zilog Z80230 - Manual (Page 121)

SCC/ESCC
User Manual
UM010903-0515 Data Communication Modes
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flag, or an idle. This means that when two frames follow one another, the intervening flag may
simultaneously be the ending flag of the first frame and the beginning flag of the next frame. This
case is usually referred to as “Back-to-Back Frames”.
The SCC’s SDLC address field is eight bits long and is used to designate which receiving stations
accept a transmitted message. The 8-bit address allows up to 254 (00000001 through 11111110)
stations to be addressed uniquely or a global address (11111111) is used to broadcast the message
to all stations. Address 0 (00000000) is usually used as a Test packet address.
The control field of a SDLC frame is typically 8 bits, but can be any length. The control field is
transparent to the SCC and is treated as normal data by the transmit and receive logic.
The information field is not restricted in format or content and can be of any reasonable length
(including zero). Its maximum length is that which is expected to arrive at the receiver error-free
most of the time. Hence, the determination of maximum length is a function of the communication
channel’s error rate. Usually the upper layer of the protocol specifies the packet size. Although the
data is always written/read in a given character size, the Residue Code feature provides the mech-
anism to read any number of bits at the end of the frame that do not make up a full character. This
allows for the data field to be an arbitrary number of bits long.
The frame check field is used to detect errors in the received address, control and information
fields. The method used to test if the received data matches the transmitted data, is called a Cyclic
Redundancy Check (CRC). The SCC has an option to select between two CRC polynomials, and
in SDLC mode only the CRC-CCITT polynomial is used because the transmitter in the SCC auto-
matically inverts the CRC before transmission. To compensate for this, the receiver checks the
CRC result for the bit pattern 0001110100001111. This is consistent with bit-oriented protocols
such as SDLC, HDLC, and ADCCP and the others.
There are two unique bit patterns in SDLC mode besides the flag sequence. They are the Abort
and EOP (End of Poll) sequence. An Abort is a sequence of seven to thirteen consecutive 1s and is
used to signal the premature termination of a frame. The EOP is the bit pattern 11111110, which is
used in loop applications as a signal to a secondary station that it may begin transmission.
SDLC mode is selected by setting bit D5 of WR4 to 1 and bits D4, D3, and D2 of WR4 to 0. In
addition, the flag sequence is written to WR7. Additional control bits for SDLC mode are located
in WR10 and WR7' (85X30).
SDLC Transmit
In SDLC mode, the transmitter moves characters from the transmitter buffer (on the ESCC, four-
byte transmitter FIFO) to the Transmit Shift register, through the zero inserter and out to the TxD
pin. The insertion of zero is completely transparent to the user. Zero insertion is done to all trans-
mitted characters except the flag and abort.
A SDLC frame must have the 01111110 (7E Hex) flag sequence transmitted before the data. This
is done automatically by the SCC by programming WR7 with 7EH as part of the device initializa-
tion, enabling the transmitter, and then writing data. If the SCC is programmed to idle Mark
(WR10 D3=1), special consideration must be taken to transmit the opening flag. Ordinarily, it is