Zilog Z80230 - Manual (Page 51)

SCC/ESCC
User Manual
UM010903-0515 Interfacing the SCC/ESCC
44
Interrupt Acknowledge
The SCC is flexible with its interrupt method. The interrupt may be acknowledged with a vector
transferred, acknowledged without a vector, or not acknowledged at all.
Interrupt Without Acknowledge
In this mode, the Interrupt Acknowledge signal does not have to be generated. This allows a sim-
pler hardware design that does not have to meet the interrupt acknowledge timing. Soon after the
INT goes active, the interrupt controller jumps to the interrupt routine. In the interrupt routine, the
code must read RR2 from Channel B to read the vector including status. When the vector is read
from Channel B, it always includes the status regardless of the VIS bit (WR9 bit 0). The status
given will decode the highest priority interrupt pending at the time it is read. The vector is not
latched so that the next read could produce a different vector if another interrupt occurs. The regis-
ter is disabled from change during the read operation to prevent an error if a higher interrupt
occurs exactly during the read operation.
Once the status is read, the interrupt routine must decode the interrupt pending, and clear the con-
dition. Removing the interrupt condition clears the IP and brings /INT inactive (open-drain), as
long as there are no other IP bits set. For example, writing a character to the transmit buffer clears
the transmit buffer empty IP.
When the interrupt IP, decoded from the status, is cleared, RR2 can be read again. This allows the
interrupt routine to clear all of the IP’s within one interrupt request to the CPU.
Interrupt With Acknowledge
After the SCC brings /INT active, the CPU can respond with a hardware acknowledge cycle by
bringing /INTACK active. After enough time has elapsed to allow the daisy chain to settle (see AC
Spec #38), the SCC sets the IUS bit for the highest priority IP. If the No Vector bit is reset (WR9
D1=0), the SCC then places the interrupt vector on the data bus during a read. To speed the inter-
rupt response time, the SCC can modify 3 bits in the vector to indicate the source of the interrupt.
To include the status, the VIS bit, WR9 D0, is set. The service routine must then clear the inter-
rupting condition. For example, writing a character to the transmit buffer clears the transmit buffer
empty IP. After the interrupting condition is cleared, the routine can read RR3 to determine if any
other IP’s are set and take the appropriate action to clear them. At the end of the interrupt routine,
a Reset IUS command (WR0) is issued to unlock the daisy chain and allow lower-priority inter-
rupt requests. This is the only way, short of a software or hardware reset, that an IUS bit is reset.
If the No Vector bit is set (WR9 D1=1), the SCC will not place the vector on the data bus. An inter-
rupt controller must then vector the code to the interrupt routine. The interrupt routine reads RR2
from Channel B to read the status. This is similar to an interrupt without an acknowledge, except
the IUS is set and the vector will not change until the Reset IUS command in RR0 is issued.
Software Interrupt Acknowledge (CMOS/ESCC)
An interrupt acknowledge cycle can be done in software for those applications which use an exter-
nal interrupt controller or which cannot generate the /INTACK signal with the required timing. If
WR9 D5 is set, reading register two, RR2, results in an interrupt acknowledge cycle to be exe-