Zilog Z80230 - Manual (Page 39)

SCC/ESCC
User Manual
UM010903-0515 Interfacing the SCC/ESCC
32
Z85C30 Register Enhancement
The Z85C30 has an enhancement to the NMOS Z8530 register set, which is the addition of a
10x19 SDLC Frame Status FIFO. When WR15 bit D2=1, the SDLC Frame Status FIFO is
enabled, and it changes the functionality of RR6 and RR7. See SDLC Frame Status FIFO on page
126 for more details on this feature.
Z85C30/Z85230/L Register Enhancements
In addition to the enhancements mentioned in Z85C30 Register Enhancement on page 32, the
85C30/85230/L provides several enhancements to the SCC register set. These include the addition
of Write Register 7 Prime (WR7'), the ability to read registers that are write-only in the SCC.
Write Register 7' is addressed by setting WR15, D0=1 and then addressing WR7. Figure and
Figure on page 33 displays the register bit location of the six features enabled through this register
0 0 1 0 WR10B RR10B RR10B RR10B
0 0 1 1 WR11B (RR15B) (RR15B) (WR10B)
0 1 0 0 WR12B RR12B RR12B RR12B
0 1 0 1 WR13B RR13B RR13B RR13B
0 1 1 0 WR14B RR14B RR14B (WR7’B)
0 1 1 1 WR15B RR15B RR15B RR15B
1 0 0 0 WR8A RR8A RR8A RR8A
1 0 0 1 WR9 (RR13A) (RR13A) (WR3A)
1 0 1 0 WR10A RR10A RR10A RR10A
1 0 1 1 WR11A (RR15A) (RR15A) (WR10A)
1 1 0 0 WR12A RR12A RR12A RR12A
1 1 0 1 WR13A RR13A RR13A RR13A
1 1 1 0 WR14A RR14A RR14A (WR7’A)
1 1 1 1 WR15A RR15A RR15A RR15A
Notes
1. WR15 bit D2 enables status FIFO function. (Not available on NMOS).
2. WR7' bit D6 enables extend read function. (Only on ESCC and 85C30).
Z85X30 Register Map (Continued)
Read 8530
85C30/230
85C30/230 WR15 D2=1
A//B PNT2 PNT1 PNT0 WRITE WR15 D2 = 0 WR15 D2=1 WR7' D6=1