Zilog Z80230 - Manual (Page 261)

SCC/ESCC
User Manual
UM010903-0515 Application Notes
254
J18 connects Pin 1 of both sockets to either A16 or V
CC
. For 2764s, 27128s, and 27256s,
Pin 1 is V
PP
which may require a high voltage and/or draw more current than a normal
logic input.
For 2764s and 27128s, a similar jumper might be provided in some designs for pin 27
(PGM). As long as the address for UCS is programmed as described in the next paragraph,
A15 (which is connected to pin 27) is High whenever UCS is Low, so that 2764s and 27128s
operate correctly.
The first code executed after Reset must program the 80186s Chip Select Control Registers to set
up the address ranges for which outputs like UCS and PCS6-PCS0 are asserted. In particular, the
UMCS register (address
A0H
within the 80186’s Peripheral Control Block) must be programmed
to correspond to the size of the EPROMs used as listed in Table .
The three LSBs of the above UMCS values are all 100, which signifies no external Ready/WAIT
is used and no wait states are required. If the EPROMS are not fast enough for no-wait-state oper-
ation, making the three LSBs 101, 110, or 111 extends EPROM cycles by 1, 2, or 3 wait states,
respectively.
RAM
Six 32-pin sockets are provided. These sockets must be populated in pairs, starting with the lower-
numbered sockets to allow for 16-bit accesses. V
CC
is provided at both Pin 32 and Pin 30 so that
28-pin 32K x 8 SRAMs can be installed in Pins 3-30 of the sockets. Jumper block J19 allows
decoding of the Chip Select signals from A17-A16 for 32K x 8 SRAMs or from A19-A18 for
128K x 8 SRAMS.
Table lists the 6 standard memory populations.
EPROM Address Ranges
UMCS Value EPROM Address Range
2764 FC3C
FC000-FFFFF
27128 F83C
F8000-FFFFF
27256 F03C
F0000-FFFFF
27512 E03C
E0000-FFFFF
Standard Memory Populations
One pair of 32K x 8
devices
64 KB at
00000-
0FFFF
Two pair of 32K x 8
devices
128 KB at
00000-
1FFFF
Three pair of 32K x 8
devices
192 KB at
00000-
2FFFF
Note: