Zilog Z80230 - Manual (Page 103)

SCC/ESCC
User Manual
UM010903-0515 Data Communication Modes
96
D2 also is affected by the state of WR7' bit D5. The All Sent bit, bit D0 of RR1, can be polled to
determine when the last bit of transmit data has cleared the TxD pin.
The number of transmit interrupts can be minimized by setting bit D5 of WR7' to one and writing
four bytes to the transmitter for each transmit interrupt. This requires that the system response to
interrupt is less than the time it takes to transmit one byte at the programmed baud rate. If the sys-
tem’s interrupt response time is too long to use this feature, bit D5 of WR7' should be reset to 0.
Then, poll the TBE bit and poll after each data write to test if there is space in the Transmit FIFO
for more data.
For details about the transmit DMA and transmit interrupts, see Transmit Interrupts and Transmit
Buffer Empty Bit on page 49.
Asynchronous Receive
Asynchronous mode is selected by specifying the number of stop bits per character in bits D3 and
D2 of WR4. This selection applies only to the transmitter, however, as the receiver always checks
for one stop bit. If after character assembly the receiver finds this stop bit to be a 0, the Framing
Error bit in the receive error FIFO is set at the same time that the character is transferred to the
receive data FIFO. This error bit accompanies the data to the exit location (CPU side) of the
Receive FIFO, where it is a special receive condition. The Framing Error bit is not latched, so it
must be read in RR1 before the accompanying data is read.
The number of bits per character is controlled by bits D7 and D6 of WR3. Five, six, seven or eight
bits per character may be selected via these two bits. Data is right justified with the unused bits set
to 1s. An additional bit, carrying parity information, may be selected by setting bit D0 of WR4 to
1. Note that this also enables parity for the transmitter. The parity sense is selected by bit D1 of
WR4. If this bit is set to 1, the received character is checked for even parity, and if set to 0, the
received character is checked for odd parity. The additional bit per character that is parity is trans-
ferred to the receive data FIFO along with the data, if the data plus parity is eight bits or less. The
parity error bit in the receive error FIFO may be programmed to cause special receive interrupts by
setting bit D2 of WR1 to 1. Once set, this error bit is latched and remains active until an Error
Reset command has been issued.
Since errors apply to specific characters, it is necessary that error information moves alongside the
data that it refers to. This is implemented in the SCC with an error FIFO in parallel with the data
FIFO. The three error conditions that the receiver checks for in Asynchronous mode are:
• Framing errors—When a character’s stop bit is a 0.
• Parity errors—The parity bit of a character disagrees with the sense programmed in WR4.
• Overrun errors—When the Receive FIFO overflows.
If interrupts are not used to transfer data, the Parity Error, Framing Error, and Overrun Error bits in
RR1 should be checked before the data is removed from the receive data FIFO, because reading
data pops up the error information stored in the Error FIFO.