Zilog Z80230 - Manual (Page 244)

SCC/ESCC
User Manual
UM010903-0515 Application Notes
237
Software Considerations
Based on the previous discussion, it is necessary to program the Z180 internal registers, as fol-
lows, before system checkout:
• Z80 ® mode of operation - Clear /M1E bit in OMCR register to zero (to provide expansion
for Z80 peripherals).
• Z80 compatible mode - Clear IOC bit in OMCR register to zero.
• Put one wait state in memory cycle, and no wait state for I/O cycle DMCR register bits 7
and 6 to ‘1’ and bits 5 and 4 to ‘0’.
SCC Read Cycle Proof
Read cycle checking is first because it is the simplest operation. The SCC Read cycle is checked
by reading the bits in RR0. First, the SCC is hardware reset by simultaneously pulling /RD and /
WR LOW (The circuit above includes the circuit for this). Then, reading out the Read Register 0
returns:
D7-D0 = 01xxx100b
Bit D2, D6:1
Bit D7, D1, D0:0
Bit D5: Reflects /CTS pin
Bit D4: Reflects /SYNC
Bit D3: Reflects /DCD pin
SCC Write Cycle Proof
Write cycle checking involves writing to a register and reading back the results to the registers
which return the written value. The Time Constant registers (WR12 and WR13) and External/Sta-
tus Interrupt Enable register (WR15) are on the SCC.
Interrupt Acknowledge Cycle
Checking an Interrupt Acknowledge (/INTACK) cycle consists of several steps. First, the SCC
makes an Interrupt Request (/INT) to the Z180. When the processor is ready to service the inter-
rupt, it shows an Interrupt Acknowledge
(/INTACK) cycle. The SCC then puts an 8-bit vector on the bus and the Z180 uses that vector to
get the correct service routine. The following test checks the simplest case.
First, load the Interrupt Vector Register (WR2) with a vector, disable the Vector Interrupt Status
(VIS) and enable interrupts (IE=1, MIE=1 IEI=1). Disabling VIS guarantees only one vector on
the bus. The address of the service routine corresponding to the 8-bit vector number loads the
Z180 vector table, and the Z180 is under Interrupt Mode 2.
Because the SCC Interrupt Pending bit (IP) cannot be set, setting an interrupt sequence is difficult.
An interrupt is generated indirectly via the CTS pin by enabling the following explanation.
Enable interrupt by /CTS (WR15,
20h
), External/Status Interrupt Enable (WR1,
01h
), and Mas-
ter Interrupt Enable (WR9,
08h
). Any change on the /CTS pin begins the interrupt sequence. The
interrupt is re-enabled by Reset External/Status Interrupt (WR0,
10h
) and Reset Highest IUS