Zilog Z80230 - Manual (Page 24)

SCC/ESCC
User Manual
UM010903-0515 Interfacing the SCC/ESCC
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Interfacing the SCC/ESCC
Introduction
This chapter covers the system interface requirements with the SCC. Timing requirements for both
devices are described in a general sense here, and the user should refer to the SCC Product Speci-
fication for detailed AC/DC parametric requirements.
The ESCC and the 85C30 have an additional register, Write Register Seven Prime (WR7'). Its fea-
tures include the ability to read WR3, WR4, WR5, WR7', and WR10. Both the ESCC and the
85C30 have the ability to deassert the /DTR//REG pin quickly to ease DMA interface design.
Additionally, the Z85230/L features a relaxed requirement for a valid data bus when the /WR pin
goes Low. The effects of the deeper data FIFOs should be considered when writing the interrupt
service routines. The user should read the sections which follow for details on these features.
Z80X30 Interface Timing
The Z-Bus compatible SCC is suited for system applications with multiplexed address/data buses
similar to the Z8 ® , Z8000, and Z280.
Two control signals, /AS and /DS, are used by the Z80X30 to time bus transactions. In addition,
four other control signals (/CS0, CS1, R//W, and /INTACK) are used to control the type of bus
transaction that occurs. A bus transaction is initiated by /AS; the rising edge latches the register
address on the Address/Data bus and the state of /INTACK and /CS0.
In addition to timing bus transactions, /AS is used by the interrupt section to set the Interrupt Pend-
ing (IP) bits.
Because of this, /AS must be kept cycling for the interrupt section to function properly.
The Z80X30 generates internal control signals in response to a register access. Since /AS and /DS
have no phase relationship with PCLK, the circuit generating these internal control signals pro-
vides time for metastable conditions to disappear. This results in a recovery time related to PCLK.
This recovery time applies only to transactions involving the Z80X30, and any intervening trans-
actions are ignored. This recovery time is four PCLK cycles, measured from the falling edge of /
DS of one access to the SCC, to the falling edge of /DS for a subsequent access.
Z80X30 Read Cycle Timing
The read cycle timing for the Z80X30 is displayed in Figure . R//W must be High before /DS falls
to indicate a read The register address on AD7-AD0, as well as the state of cycle. The Z80X30
data bus drivers are enabled while CS1 /CS0 and /INTACK, are latched by the rising edge of /AS.
is High and /DS is Low.