Altera IP Compiler for PCI Express - Manual (Page 102)

5–16 Chapter 5: IP Core Interfaces
Avalon-ST Interface
IP Compiler for PCI Express User Guide August 2014 Altera Corporation
tx_st_sop<n> 1 I
start of
packet
When asserted with tx_st_valid<n>, indicates first
cycle of a TLP.
tx_st_eop<n> 1 I
end of
packet
When asserted with tx_st_valid<n>, indicates final
cycle of a TLP.
tx_st_empty<n> 1 I empty
Indicates that the TLP ends in the lower 64 bits of
tx_st_data<n>
. Valid only when tx_st_eop<n> is
asserted.This signal only applies to 128-bit mode in the
hard IP implementation.
When tx_st_eop<n> is asserted and tx_st_empty<n>
has value 1, tx_st_data[63:0] holds valid data but
tx_st_data[127:64]
does not hold valid data.
When tx_st_eop<n> is asserted and tx_st_empty<n>
has value 0, tx_st_data[127:0] holds valid data.
tx_st_err<n> 1 I error
Indicates an error on transmitted TLP. This signal is used
to nullify a packet. It should only be applied to posted and
completion TLPs with payload. To nullify a packet, assert
this signal for 1 cycle after the SOP and before the EOP.
In the case that a packet is nullified, the following packet
should not be transmitted until the next clock cycle. This
signal is not available on the ×8 Soft IP. tx_st_err is not
available for packets that are 1 or 2 cycles long.
Refer to Figure 5–21 on page 5–20 for a timing diagram
that illustrates the use of the error signal. Note that it
must be asserted while the valid signal is asserted.
Component Specific Signals
tx_fifo_full<n> 1 O
component
specific
Indicates that the adapter TX FIFO is almost full.
tx_fifo_empty<n> 1 O
component
specific
Indicates that the adapter TX FIFO is empty.
tx_fifo_rdptr<n>[3:0] 4 O
component
specific
This is the read pointer for the adaptor TX FIFO.
tx_fifo_wrptr[3:0] 4 O
component
specific
This is the write pointer for the adaptor TX FIFO.
Table 5–4. 64- or 128-Bit Avalon-ST TX Datapath (Part 2 of 3)
Signal Width Dir
Avalon-ST
Type
Description