Altera IP Compiler for PCI Express - Manual (Page 197)

August 2014 Altera Corporation IP Compiler for PCI Express User Guide
11. Flow Control
Throughput analysis requires that you understand the Flow Control Loop, shown in
“Flow Control Update Loop” on page 11–2 . This section discusses the Flow Control
Loop and strategies to improve throughput. It covers the following topics:
■ Throughput of Posted Writes
■ Throughput of Non-Posted Reads
Throughput of Posted Writes
The throughput of posted writes is limited primarily by the Flow Control Update loop
shown in
Figure 11–1 . If the requester of the writes sources the data as quickly as
possible, and the completer of the writes consumes the data as quickly as possible,
then the Flow Control Update loop may be the biggest determining factor in write
throughput, after the actual bandwidth of the link.
Figure 11–1 shows the main components of the Flow Control Update loop with two
communicating PCI Express ports:
■ Write Requester
■ Write Completer
As the PCI Express specification describes, each transmitter, the write requester in this
case, maintains a credit limit register and a credits consumed register. The credit
limit
register is the sum of all credits issued by the receiver, the write completer in
this case. The credit limit register is initialized during the flow control initialization
phase of link initialization and then updated during operation by Flow Control (FC)
Update DLLPs. The credits consumed register is the sum of all credits consumed by
packets transmitted. Separate credit limit and credits consumed registers exist for
each of the six types of Flow Control:
■ Posted Headers
■ Posted Data
■ Non-Posted Headers
■ Non-Posted Data
■ Completion Headers
■ Completion Data
August 2014
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