Altera IP Compiler for PCI Express - Manual (Page 156)

6–8 Chapter 6: Register Descriptions
PCI Express Avalon-MM Bridge Control Register Content
IP Compiler for PCI Express User Guide August 2014 Altera Corporation
A PCI Express interrupt can be enabled for any of the conditions registered in the PCI
Express interrupt status register by setting the corresponding bits in the
Avalon-MM-to-PCI Express interrupt enable register (
Table 6–14 ). Either MSI or
legacy interrupts can be generated as explained in the section “Generation of PCI
Express Interrupts” on page 4–22 .
PCI Express Mailbox Registers
A Qsys-generated IP Compiler for PCI Express can have as many as 16 individual
incoming interrupt signals, and requires a separate interrupt enable bit for each
signal.
The PCI Express root complex typically requires write access to a set of PCI
Express-to-Avalon-MM mailbox registers and read-only access to a set of
Avalon-MM-to-PCI Express mailbox registers. Eight mailbox registers are available.
[21] A2P_MAILBOX_INT5 RW1C 1 when the A2P_MAILBOX5 is written to
[20] A2P_MAILBOX_INT4 RW1C 1 when the A2P_MAILBOX4 is written to
[19] A2P_MAILBOX_INT3 RW1C 1 when the A2P_MAILBOX3 is written to
[18] A2P_MAILBOX_INT2 RW1C 1 when the A2P_MAILBOX2 is written to
[17] A2P_MAILBOX_INT1 RW1C 1 when the A2P_MAILBOX1 is written to
[16] A2P_MAILBOX_INT0 RW1C 1 when the A2P_MAILBOX0 is written to
[15:0] (Qsys) AVL_IRQ_ASSERTED[15:0] RO
Current value of the Avalon-MM interrupt (IRQ) input
ports to the Avalon-MM RX master port:
0 – Avalon-MM IRQ is not being signaled.
1 – Avalon-MM IRQ is being signaled.
A Qsys-generated IP Compiler for PCI Express has as
many as 16 distinct IRQ input ports. Each
AVL_IRQ_ASSERTED[]
bit reflects the value on the
corresponding IRQ input port.
Table 6–13. Avalon-MM to PCI Express Interrupt Status Register (Part 2 of 2) Address: 0x0040
Bit Name Access Description
Table 6–14. Avalon-MM to PCI Express Interrupt Enable Register Address: 0x0050
Bits Name Access Description
[31:24] Reserved — —
[23:16] A2P_MB_IRQ RW
Enables generation of PCI Express interrupts when a
specified mailbox is written to by an external
Avalon-MM master.
[15:0] (Qsys) AVL_IRQ [15:0] RW
Enables generation of PCI Express interrupts when a
specified Avalon-MM interrupt signal is asserted. Your
Qsys system may have as many as 16 individual input
interrupt signals.