Altera IP Compiler for PCI Express - Manual (Page 229)

Chapter 14: External PHYs 14–9
External PHY Support
August 2014 Altera Corporation IP Compiler for PCI Express User Guide
8-bit PHY Interface Signals
Table 14–3 summarizes the external I/O signals for the 8-bit PIPE interface modes.
Depending on the number of lanes selected and whether the PHY mode has a TXClk,
some of the signals may not be available as noted.
rxelecidle3_ext I Pipe interface lane 3 RX electrical idle indication. Only in ×4
rxpolarity3_ext O Pipe interface lane 3 RX polarity inversion control. Only in ×4
rxstatus3_ext[1:0] I Pipe interface lane 3 RX status flags. Only in ×4
rxvalid3_ext I Pipe interface lane 3 RX valid indication. Only in ×4
txcompl3_ext O Pipe interface lane 3 TX compliance control. Only in ×4
txdata3_ext[15:0] O
Pipe interface lane 3 TX data signals, carries the
parallel transmit data.
Only in ×4
txdatak3_ext[1:0] O Pipe interface lane 3 TX data K-character flags. Only in ×4
txelecidle3_ext O Pipe interface lane 3 TX electrical Idle Control. Only in ×4
Table 14–2. 16-bit PHY Interface Signals (Part 3 of 3)
Signal Name Direction Description Availability
Table 14–3. 8-bit PHY Interface Signals (Part 1 of 2)
Signal Name Direction Description Availability
pcie_rstn I IP Compiler for PCI Express reset signal, active low. Always
phystatus_ext I
PIPE interface phystatus signal. Signals the completion
of the requested operation.
Always
powerdown_ext[1:0] O
PIPE interface powerdown signal, Used to request that
the PHY enter the specified power state.
Always
refclk I
Input clock connected to the PIPE interface pclk signal
from the PHY. Clocks all of the status and data signals.
Depending on whether this is an SDR or DDR interface
this clock will be either 250 MHz or 125 MHz.
Always
pipe_txclk O
Source synchronous transmit clock signal for clocking
TX data and control signals going to the PHY. Only in modes that
have the TXClk
rxdata0_ext[7:0] I
Pipe interface lane 0 RX data signals, carries the parallel
received data.
Always
rxdatak0_ext I Pipe interface lane 0 RX data K-character flag. Always
rxelecidle0_ext I Pipe interface lane 0 RX electrical idle indication. Always
rxpolarity0_ext O Pipe interface lane 0 RX polarity inversion control. Always
rxstatus0_ext[1:0] I Pipe interface lane 0 RX status flags. Always
rxvalid0_ext I Pipe interface lane 0 RX valid indication. Always
txcompl0_ext O Pipe interface lane 0 TX compliance control. Always
txdata0_ext[7:0] O
Pipe interface lane 0 TX data signals, carries the parallel
transmit data.
Always
txdatak0_ext O Pipe interface lane 0 TX data K-character flag. Always
txelecidle0_ext O Pipe interface lane 0 TX electrical idle control. Always
rxdata1_ext[7:0] I
Pipe interface lane 1 RX data signals, carries the parallel
received data.
Only in ×4