Altera IP Compiler for PCI Express - Manual (Page 289)

August 2014 Altera Corporation IP Compiler for PCI Express User Guide
16. Qsys Design Example
The Qsys design example provides detailed step-by-step instructions to generate a
Qsys system. The Qsys design flow supports the following IP Compiler for PCI
Express features:
■ Hard IP implementation
■ Arria II GX and Stratix IV GX devices
■ 125 MHz Gen1 ×1 and ×4 with a 64-bit interface, 250 MHz Gen2 ×1 with a 64-bit
interface
■ Dynamic bus sizing as opposed to native addressing
The IP Compiler for PCI Express installs with supporting files for design examples
that support the following two IP Compiler for PCI Express variations:
■ Gen1:×8 IP Compiler for PCI Express hard IP implementation that targets a
Stratix IV GX device
■ Gen1:×4 IP Compiler for PCI Express hard IP implementation that targets a
Cyclone IV GX device
This chapters walks through the Gen1:×8 design example. You can run the Gen1:×4
design example by substituting the appropriate target device, number of lanes, and
folder substitutions in the instructions in this chapter.
In this design example walkthrough, you generate a Qsys system that contains the
following components:
■ Gen1:×8 IP Compiler for PCI Express hard IP implementation that targets a
Stratix IV GX device
■ On-Chip memory
■ DMA controller
In the Qsys design flow you select the IP Compiler for PCI Express as a component.
This component supports PCI Express ×1, ×2, ×4, or ×8 endpoint applications with
bridging logic to convert PCI Express packets to Avalon-MM transactions and vice
versa. The design example in this chapter illustrates the use of a single hard IP
implementation with an embedded transceiver. The Qsys design flow does not
support an external transceiver.
August 2014
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