Altera IP Compiler for PCI Express - Manual (Page 54)

3–18 Chapter 3: Parameter Settings
IP Core Parameters
IP Compiler for PCI Express User Guide August 2014 Altera Corporation
Power Management
The Power Management page contains the parameters for setting various power
management properties of the IP core. These parameters are not available in the Qsys
design flow.
Desired
performance for
received
completions
Maximum,
High,
Medium, Low
Specifies how to configure the RX buffer size and the flow control credits:
Maximum—Provides additional space to allow for additional external delays (link
side and application side) and still allows full throughput.
If you need more buffer space than this parameter supplies, select a larger
payload size and this setting. The maximum setting increases the buffer size and
slightly increases the number of logic elements (LEs), to support a larger payload
size than is used. This is the default setting for the hard IP implementation.
Medium—Provides a moderate amount of space for received completions. Select
this option when the received completion traffic does not need to use the full link
bandwidth, but is expected to occasionally use short bursts of maximum sized
payload packets.
Low—Provides the minimal amount of space for received completions. Select
this option when the throughput of the received completions is not critical to the
system design. This is used when your application is never expected to initiate
read requests on the PCI Express links. Selecting this option minimizes the device
resource utilization.
For the hard IP implementation, this parameter is not directly adjustable. The
value set is derived from the values of Max payload size and the Desired
performance for received requests parameter.
For more information, refer to Chapter 11, Flow Control . This analysis explains
how the Maximum payload size and Desired performance for received
completions that you choose affects the allocation of flow control credits.
RX Buffer Space
Allocation (per
VC)
Read-Only
table
Shows the credits and space allocated for each flow-controllable type, based on the
RX buffer size setting. All virtual channels use the same RX buffer space allocation.
The table shows header and data credits for RX posted (memory writes) and
completion requests, and header credits for non-posted requests (memory reads).
The table does not show non-posted data credits because the IP core always
advertises infinite non-posted data credits and automatically has room for the
maximum number of dwords of data that can be associated with each non-posted
header.
The numbers shown for completion headers and completion data indicate how much
space is reserved in the RX buffer for completions. However, infinite completion
credits are advertised on the PCI Express link as is required for endpoints. The
application layer must manage the rate of non-posted requests to ensure that the RX
buffer completion space does not overflow. The hard IP RX buffer is fixed at 16
KBytes for Stratix IV GX devices and 4 KBytes for Arria II GX devices.
Table 3–12. Buffer Setup Parameters (Part 3 of 3)
Parameter Value Description