Altera IP Compiler for PCI Express - Manual (Page 226)

14–6 Chapter 14: External PHYs
External PHY Support
IP Compiler for PCI Express User Guide August 2014 Altera Corporation
<path>/ip/ip_compiler_for_pci_express/lib directory, where <path> is the
directory in which you installed the IP Compiler for PCI Express, to your project
directory. Then use the parameter editor to edit the PLL source file to set the
required phase shift. Then add the modified PLL source file to your Quartus II
project.
■ An optional 62.5 MHz TLP Slow clock is provided for ×1 implementations.
An edge detect circuit detects the relationships between the 125 MHz clock and the
250 MHz rising edge to properly sequence the 16-bit data into the 8-bit output
register.
8-bit SDR with a Source Synchronous TXClk
Figure 14–6 illustrates the implementation of the 16-bit SDR mode with a source
synchronous TXClk. It is included in the file <variation name>.v or
<variation name>.vhd and includes a PLL. refclk (pclk from the external PHY) drives
the PLL inclock. The PLL has the following outputs:
■ A 125 MHz output derived from the 250 MHz refclk. This 125 MHz PLL output is
used as the clk125_in for the IP core.
■ A 250 MHz early output that is skewed early in relation to the refclk the 250 MHz
early clock PLL output clocks an 8-bit SDR transmit data output register.
■ An optional 62.5 MHz TLP Slow clock is provided for ×1 implementations.
Figure 14–5. 8-bit SDR Mode - 250 MHz
IP Compiler
for PCI Express
clk125_in
tlp_clk
refclk
rxdata
clk125_out
clk125_in
ENB
Q
Q
A
1
D
4
txdata
ENB
A
D
Q
1
Q
4
Mode 4
PLL
ENB
Q
Q
A
1
D
4
txdata_h
txdata_l
Edge
Detect
& Sync
clk250_early
External connection
in user logic
ENB
A
D
Q
1
Q
4
ENB
A
D
Q
1
Q
4
ENB
A
D
Q
1
Q
4
ENB
A
D
Q
1
Q
4
rxdata_h
rxdata_l
refclk (pclk) 250 MHz