Altera IP Compiler for PCI Express - Manual (Page 136)

5–50 Chapter 5: IP Core Interfaces
Avalon-MM Application Interface
IP Compiler for PCI Express User Guide August 2014 Altera Corporation
64-Bit Bursting TX Avalon-MM Slave Signals
This optional Avalon-MM bursting slave port propagates requests from the
interconnect fabric to the full-featured IP Compiler for PCI Express. Requests from the
interconnect fabric are translated into PCI Express request packets. Incoming requests
can be up to 512 bytes in Qsys systems. For better performance, Altera recommends
using smaller read request size (a maximum 512 bytes).
Table 5–25 lists the TX slave interface ports.
Table 5–25. Avalon-MM TX Slave Interface Signals
Signal Name in
Qsys
I/O Description
TxsChipSelect_i/Txs_chipselect I
The system interconnect fabric asserts this signal to select the TX
slave port.
TxsRead_i/Txs_read I
Read request asserted by the system interconnect fabric to
request a read.
TxsWrite_i/Txs_write I
Write request asserted by the system interconnect fabric to
request a write.
The IP Compiler for PCI Express requires that the Avalon-MM
master assert this signal continuously from the first data phase
through the final data phase of the burst. The Avalon-MM master
application software must guarantee the data can be passed to
the interconnect fabric with no pauses. This behavior is most
easily implemented with a store and forward buffer in the
Avalon-MM master.
TxsAddress_i[TXS_ADDR_WIDTH-1:0]/
Txs_address[TXS_ADDR_WIDTH-1:0]
I
Address of the read or write request from the external Avalon-MM
master. This address translates to 64-bit or 32-bit PCI Express
addresses based on the translation table. The TXS_ADDR_WIDTH
value is determined when the system is created.
TxsBurstCount_i[9:0]/
Txs_burstcount[9:0]
I
Asserted by the system interconnect fabric indicating the amount
of data requested. The count unit is the amount of data that is
transfered in a single data phase, that is, the width of the bus. The
amount of data requested is limited to 4 KBytes, the maximum
data payload supported by the PCI Express protocol. In Qsys
systems, the burst count is limited to 512 bytes.
TxsWriteData_i[63:0]/
Txs_writedata[63:0]
I
Write data sent by the external Avalon-MM master to the TX
slave port.
TxsByteEnable_i[7:0]/
Txs_byteenable[7:0]
I
Write byte enable for data. A burst must be continuous. Therefore
all intermediate data phases of a burst must have byte enable
value 0xFF. The first and final data phases of a burst can have
other valid values.
TxsReadDataValid_o/Txs_readdatavalid O Asserted by the bridge to indicate that read data is valid.
TxsReadData_o[63:0]/
Txs_readdata[63:0]
O
The bridge returns the read data on this bus when the RX read
completions for the read have been received and stored in the
internal buffer.
TxsWaitRequest_o/Txs_waitrequest O
Asserted by the bridge to hold off write data when running out of
buffer space. If this signal is asserted during an operation, the
master should maintain the TxsRead_i signal (or TxsWrite_i
signal and TxsWriteData_i) stable until after TxsWaitRequest
is deasserted.