Altera IP Compiler for PCI Express - Manual (Page 211)

August 2014 Altera Corporation IP Compiler for PCI Express User Guide
13. Reconfiguration and Offset
Cancellation
This chapter describes features of the IP Compiler for PCI Express that you can use to
reconfigure the core after power-up. It includes the following sections:
■ Dynamic Reconfiguration
■ Transceiver Offset Cancellation
Dynamic Reconfiguration
The IP Compiler for PCI Express reconfiguration block allows you to dynamically
change the value of configuration registers that are read-only at run time.The IP
Compiler for PCI Express reconfiguration block is only available in the hard IP
implementation for the Arria II GX, Arria II GZ, Cyclone IV GX, HardCopy IV GX
and Stratix IV GX devices. Access to the IP Compiler for PCI Express reconfiguration
block is available when you select Enable for the PCIe Reconfig option on the System
Settings
page using the parameter editor. You access this block using its Avalon-MM
slave interface. For a complete description of the signals in this interface, refer to “IP
Core Reconfiguration Block Signals—Hard IP Implementation” on page 5–38 .
The IP Compiler for PCI Express reconfiguration block provides access to read-only
configuration registers, including configuration space, link configuration, MSI and
MSI-X capabilities, power management, and advanced error reporting.
The procedure to dynamically reprogram these registers includes the following three
steps:
1. Bring down the PCI Express link by asserting the pcie_reconfig_rstn reset signal,
if the link is already up. (Reconfiguration can occur before the link has been
established.)
2. Reprogram configuration registers using the Avalon-MM slave PCIe Reconfig
interface.
3. Release the npor reset signal.
1
You can use the LMI interface to change the values of configuration registers that are
read/write at run time. For more information about the LMI interface, refer to
“LMI
Signals—Hard IP Implementation” on page 5–37 .
August 2014
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