Altera IP Compiler for PCI Express - Manual (Page 84)

4–26 Chapter 4: IP Core Architecture
Completer Only PCI Express Endpoint Single DWord
IP Compiler for PCI Express User Guide August 2014 Altera Corporation
Only one type of interrupt can be enabled at a time. However, to change the selection
of MSI or legacy interrupts during operation, software must ensure that no interrupt
request is dropped. Therefore, software must first enable the new selection and then
disable the old selection. To set up legacy interrupts, software must first clear the
Interrupt
Disable bit and then clear the MSI enable bit. To set up MSI interrupts,
software must first set the MSI enable bit and then set the Interrupt Disable bit.
Generation of Avalon-MM Interrupts
Generation of Avalon-MM interrupts requires the instantiation of the CRA slave
module where the interrupt registers and control logic are implemented. The CRA
slave port has an Avalon-MM Interrupt (CraIrq_irq in Qsys systems) output signal.
A write access to an Avalon-MM mailbox register sets one of the P2A_MAILBOX_INT<n>
bits in the
“PCI Express to Avalon-MM Interrupt Status Register Address: 0x3060”
on page 6–11 and asserts the CraIrq_o or CraIrq_irq output, if enabled. Software can
enable the interrupt by writing to the “PCI Express to Avalon-MM Interrupt Enable
Register Address: 0x3070” on page 6–11 through the CRA slave. After servicing the
interrupt, software must clear the appropriate serviced interrupt status bit in the
PCI-Express-to-Avalon-MM Interrupt Status register and ensure that there is no
other interrupt pending.
Completer Only PCI Express Endpoint Single DWord
The completer only single dword endpoint is intended for applications that use the
PCI Express protocol to perform simple read and write register accesses from a host
CPU. The completer only single dword endpoint is a hard IP implementation
available for Qsys systems, and includes an Avalon-MM interface to the application
layer. The Avalon-MM interface connection in this variation is 32 bits wide. This
endpoint is not pipelined; at any time a single request can be outstanding.
The completer-only single dword endpoint supports the following requests:
■ Read and write requests of a single dword (32 bits) from the root complex
■ Completion with completer abort status generation for other types of non-posted
requests
■ INTX or MSI support with one Avalon-MM interrupt source
As this figure illustrates, the IP Compiler for PCI Express links to a PCI Express root
complex. A bridge component in the IP Compiler for PCI Express includes IP
Compiler for PCI Express TX and RX blocks, an Avalon-MM RX master, and an
interrupt handler. The bridge connects to the FPGA fabric using an Avalon-MM
interface. The following sections provide an overview of each block in the bridge.
IP Compiler for PCI Express RX Block
The IP Compiler for PCI Express RX control logic interfaces to the hard IP block to
process requests from the root complex. It supports memory reads and writes of a
single dword. It generates a completion with Completer Abort (CA) status for reads
greater than four bytes and discards all write data without further action for write
requests greater than four bytes.