Altera IP Compiler for PCI Express - Manual (Page 35)

Chapter 2: Getting Started 2–19
Compiling the Design
August 2014 Altera Corporation IP Compiler for PCI Express User Guide
Specifying QSF Constraints
This section describes two additional constraints to improve performance in specific
cases.
■ Constraints for Stratix IV GX ES silicon–add the following constraint to your .qsf
file:
set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to
*wire_central_clk_div*_coreclkout
This constraint aligns the PIPE clocks (core_clk_out) from each quad to reduce
clock skew in ×8 variants.
■ Constraints for design running at frequencies higher than 250 MHz:
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
This constraint improves performance for designs in which asynchronous signals
in very fast clock domains cannot be distributed across the FPGA fast enough due
to long global network delays. This optimization performs automatic pipelining of
these signals, while attempting to minimize the total number of registers inserted.
Compiling the Design
To test your IP Compiler for PCI Express in hardware, your initial Quartus II
compilation includes all of the directories shown in
Figure 2–5 . After you have fully
tested your customized design, you can exclude the testbench directory from the
Quartus II compilation.
On the Processing menu, click Start Compilation to compile your design.
Pin Assignments for the Stratix IV (EP4SGX230KF40C2) Development Board (continued)
set_instance_assignment -name IO_STANDARD "2.5 V" -to usr_sw[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to usr_sw[1]
set_instance_assignment -name IO_STANDARD "2.5 V" -to usr_sw[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to usr_sw[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to usr_sw[4]
set_instance_assignment -name IO_STANDARD "2.5 V" -to usr_sw[5]
set_instance_assignment -name IO_STANDARD "2.5 V" -to usr_sw[6]
set_instance_assignment -name IO_STANDARD "2.5 V" -to usr_sw[7]
set_instance_assignment -name IO_STANDARD "2.5 V" -to
lane_active_led[0]
set_instance_assignment -name IO_STANDARD "2.5 V" -to
lane_active_led[2]
set_instance_assignment -name IO_STANDARD "2.5 V" -to
lane_active_led[3]
set_instance_assignment -name IO_STANDARD "2.5 V" -to L0_led
set_instance_assignment -name IO_STANDARD "2.5 V" -to alive_led
set_instance_assignment -name IO_STANDARD "2.5 V" -to comp_led
# Note reclk_free uses 100 MHz input
# On the S4GX Dev kit make sure that
# SW4.5 = ON
# SW4.6 = ON
set_instance_assignment -name IO_STANDARD LVDS -to free_100MHz
set_location_assignment PIN_AV22 -to free_100MHz