Altera IP Compiler for PCI Express - Manual (Page 301)

Chapter 16: Qsys Design Example 16–13
Simulating the Qsys System
August 2014 Altera Corporation IP Compiler for PCI Express User Guide
Table 16–13 lists the files that are generated in your Quartus II project directory. In this
design example, the project directory is C:\projects\s4gx_gen1x8_qsys and the Qsys
system directory is hip_s4gx_gen1x8_qsys.
Simulating the Qsys System
Qsys creates a top-level testbench named
< project_dir >/ hip_s4gx_gen1x8_qsys/testbench/hip_s4gx_gen1x8_qsys_tb.qsys . This
testbench connects an appropriate BFM to each exported interface. Qsys generates the
required files and models to simulate your IP Compiler for PCI Express system.
This section of the design example walkthrough uses the following files and software:
■ The system you created using Qsys
■ The testbench created by Qsys in the
<project_dir>/ hip_s4gx_gen1x8_qsys/testbench directory. You can view this
testbench in Qsys by opening the file
< project_dir >/ hip_s4gx_gen1x8_qsys/testbench/hip_s4gx_gen1x8_qsys_tb.qsys .
■ The ModelSim-Altera Edition software
1 You can also use any other supported third-party simulator to simulate your design.
Qsys creates IP functional simulation models for all the system components. The IP
functional simulation models are the .vo or .vho files generated by Qsys in your
project directory.
f For more information about IP functional simulation models, refer to Simulating Altera
Designs in volume 3 of the Quartus II Handbook.
Table 16–13. Qsys System Generated Directories
Directory Location
Qsys system <project_dir>/hip_s4gx_gen1x8_qsys
Synthesis <project_dir>/hip_s4gx_gen1x8_qsys/synthesis
Simulation <project_dir>/hip_s4gx_gen1x8_qsys/simulation
Testbench <project_dir>/hip_s4gx_gen1x8_qsys/testbench