Altera IP Compiler for PCI Express - Manual (Page 364)

Info–4 Chapter :
Revision History
IP Compiler for PCI Express User Guide August 2014 Altera Corporation
July 2010 10.0
■ Added table specifying the Total RX buffer space, the RX Retry buffer size and Maximum
payload size for devices that include the hard IP implementation.
■ Recommended that designs specify may eventually target the HardCopy IV GX device,
specify this device as the PHY type to ensure compatibility.
■ Improved definitions for hpg_ctrler signal. This bus is only available in root port mode. In
the definition for the various bits, changed “This signal is” to “This signal should be.”
■ Removed information about Stratix GX devices. The PCI Express Compiler no longer
supports Stratix GX.
■ Removed appendix describing test_in/test_out bus. Supported bits are described in
Chapter 5, IP Core Interfaces.
■ Moved information on descriptor/data interface to an appendix. This interface is not
recommended for new designs.
■ Clarified use of tx_cred for non-posted, posted, and completion TLPs.
■ Corrected definition of Receive port error in Table 12–2 on page 12–2.
■ Removed references to the PCI Express Advisor. It is no longer supported.
■ Reorganized entire User Guide to highlight more topics and provide a complete walkthough
for the variants.
February 2010 9.1 SP1
■ Added support of Cyclone IV GX ×2.
■ Added r2c_err0 and r2c_err1 signals to report uncorrectable ECC errors for the hard IP
implementation with Avalon-ST interface.
■ Added suc_spd_neg signal for all hard IP implementations which indicates successful
negotiation to the Gen2 speed.
■ Added support for 125 MHz input reference clock (in addition to the 100 MHz input
reference clock) for Gen1 for Arria II GX, Cyclone IV GX, HardCopy IV GX, and Stratix IV GX
devices.
■ Added new entry to Table 1–9 on page 1–13. The hard IP implementation using the
Avalon-MM interface for Stratix IV GX Gen2 ×1 is available in the -2 and -3 speed grades.
■ Corrected entries in Table 9–2 on page 9–2, as follows: Assert_INTA and Deassert_INTA are
also generated by the core with application layer. For PCI Base Specification 1.1 or 2.0 hot
plug messages are not transmitted to the application layer.
■ Clarified mapping of message TLPs. They use the standard 4 dword format for all TLPs.
■ Corrected field assignments for device_id and revision_id in Table 13–1 on page 13–2.
■ Removed documentation for BFM Performance Counting in the Testbench chapter; these
procedures are not included in the release.
■ Updated definition of rx_st_bardec<n> to say that this signal is also ignored for message
TLPs. Updated Figure 5–8 on page 5–10 and Figure 5–9 on page 5–10 to show the timing of
this signal.
Date Version Changes Made SPR