Altera IP Compiler for PCI Express - Manual (Page 312)

17–4 Chapter 17: Debugging
Link and Transceiver Testing
IP Compiler for PCI Express User Guide August 2014 Altera Corporation
To support data integrity when using the reverse parallel loopback path for testing,
ensure that your system includes AC coupling between the root complex TX pins and
the endpoint RX pins on the PCI Express link.
To configure the transceiver in this loopback mode and perform PMA testing, your
AC-coupled system must follow these steps:
1. During link training, in the Configuration.LinkWidth.Start substate, the root
complex asserts the loopback bit (bit [2] of symbol 5) in TS1 and TS2 ordered sets.
2. After the endpoint enters the Loopback state successfully, the endpoint asserts the
tx_detectrxloopback signal and deasserts the txelecidle signal. The endpoint
transceiver enables the reverse parallel loopback path automatically after it detects
the assertion of the tx_detectrxloopback signal.
3. The root complex transmits 8B/10B encoded patterns to the endpoint,
interspersed with SKP ordered sets at the intervals dictated by the PCI Express
specification. Transmission of SKP ordered sets is necessary to ensure the rate
matching FIFO buffer does not underflow or overflow.
4. The root complex compares the loopback TX data with the original data it
transmitted to the endpoint, ignoring the SKP ordered sets as per the PCI Express
specification.