Altera IP Compiler for PCI Express - Manual (Page 72)

4–14 Chapter 4: IP Core Architecture
Physical Layer
IP Compiler for PCI Express User Guide August 2014 Altera Corporation
Physical Layer
The physical layer is the lowest level of the IP core. It is the layer closest to the link. It
encodes and transmits packets across a link and accepts and decodes received
packets. The physical layer connects to the link through a high-speed SERDES
interface running at 2.5 Gbps for Gen1 implementations and at 2.5 or 5.0 Gbps for
Gen2 implementations. Only the hard IP implementation supports the Gen2 rate of
5.0 Gbps.
The physical layer is responsible for the following actions:
■ Initializing the link
■ Scrambling and descrambling and 8B/10B encoding and decoding of 2.5 Gbps
(Gen1) or 5.0 Gbps (Gen2) per lane 8B/10B
■ Serializing and deserializing data
The hard IP implementation includes the following additional functionality:
■ PIPE 2.0 Interface Gen1/Gen2: 8-bit@250/500 MHz (fixed width, variable clock)
■ Auto speed negotiation (Gen2)
■ Training sequence transmission and decode
■ Hardware autonomous speed control
■ Auto lane reversal