Altera IP Compiler for PCI Express - Manual (Page 359)

Chapter : C–5
Descriptor/Data Interface
August 2014 Altera Corporation IP Compiler for PCI Express User Guide
Cyclone III Family
Table C–8 shows the typical expected performance and resource utilization of
Cyclone III (EP3C80F780C6) devices for different parameters, using the Quartus II
software, version 11.0.
Stratix II GX Devices
Table C–9 shows the typical expected performance and resource utilization of the
Stratix II and Stratix II GX (EP2SGX130GF1508C3) devices for a maximum payload of
256 bytes with different parameters, using the Quartus II software, version 11.0.
×4 125 1 6800 4600 6 12
×4 125 2 8210 5400 6 19
Table C–7. Performance and Resource Utilization, Descriptor/Data Interface - Arria GX Devices
Parameters Size
×1/ ×4
Internal
Clock (MHz)
Virtual
Channels
Combinational
ALUTs
Logic
Registers
Memory Blocks
M512 M4K
Table C–8. Performance and Resource Utilization, Descriptor/Data Interface - Cyclone III Family
Parameters Size
×1/ ×4
Internal
Clock (MHz)
Virtual
Channels
Logic
Elements
Dedicated
Registers
M9K Memory
Blocks
×1 125 1 8200 3600 6
×1 125 2 10100 4500 9
×1 (1) 62.5 1 8500 3800 25
×1 62.5 2 10200 4600
28
×4 125 1 10500 4500 12
×4 125 2 122000 5300 17
Note to Table C–8 :
(1) Max payload set to 128 bytes, the number of Tags supported set to 4, and Desired performance for received
requests and Desired performance for completions both set to Low.
Table C–9. Performance and Resource Utilization, Descriptor/Data Interface - Stratix II and
Stratix II GX Devices (Part 1 of 2)
Parameters Size
×1/ ×4
Internal
Clock (MHz)
Virtual
Channels
Combinational
ALUTs
Logic
Registers
Memory Blocks
M512 M4K
×1 125 1 5000 3500 1 9
×1 125 2 6200 4400 2 13
×4 125 1 6600 4500 5 13
×4 125 2 7600 5300 6 21