Altera IP Compiler for PCI Express - Manual (Page 191)

August 2014 Altera Corporation IP Compiler for PCI Express User Guide
10. Interrupts
This chapter covers interrupts for endpoints and root ports.
PCI Express Interrupts for Endpoints
The IP Compiler for PCI Express provides support for PCI Express legacy interrupts,
MSI interrupts, and MSI-X interrupts when configured in endpoint mode. MSI-X
interrupts are only available in the hard IP implementation endpoint variations. The
MSI, MSI-X, and legacy interrupts are mutually exclusive. After power up, the IP core
starts in INTX mode, after which time software decides whether to switch to MSI
mode by programming the MSI Enable bit of the MSI message control register
(bit [16] of 0x050) to 1 or to MSI-X mode if you turn on Implement MSI-X on the
Capabilities
page using the parameter editor. If you turn on the Implement MSI-X
option, you should implement the MSI-X table structures at the memory space
pointed to by the BARs.
To switch interrupt mode during operation, software must first enable the new mode
and then disable the previous mode, if applicable. To enable legacy interrupts when
the current interrupt mode is MSI, software must first turn off the Disable Interrupt
bit (bit [10] of the Command register at configuration space offset 0x4) and then turn off
the MSI Enable bit. To enable MSI interrupts, software must first set the MSI enable
bit and then set the Interrupt Disable bit.
f Refer to section 6.1 of PCI Express 2.0 Base Specification for a general description of PCI
Express interrupt support for endpoints.
MSI Interrupts
MSI interrupts are signaled on the PCI Express link using a single dword memory
write TLPs generated internally by the IP Compiler for PCI Express. The app_msi_req
input port controls MSI interrupt generation. When the input port asserts
app_msi_req
, it causes a MSI posted write TLP to be generated based on the MSI
configuration register values and the app_msi_tc and app_msi_num input ports.
Figure 10–1 illustrates the architecture of the MSI handler block.
Figure 10–1. MSI Handler Block
MSI Handler
Block
app_msi_req
app_msi_ack
app_msi_tc
app_msi_num
pex_msi_num
app_int_sts
cfg_msicsr[15:0]
August 2014
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