Altera IP Compiler for PCI Express - Manual (Page 161)

Chapter 6: Register Descriptions 6–13
Comprehensive Correspondence between Config Space Registers and PCIe Spec Rev 2.0
August 2014 Altera Corporation IP Compiler for PCI Express User Guide
0x0B8:0x0FC Reserved
0x094:0x0FF Root port
0x100:0x16C Virtual channel capability structure Virtual Channel Capability
0x170:0x17C Reserved
0x180:0x1FC Virtual channel arbitration table VC Arbitration Table
0x200:0x23C Port VC0 arbitration table (Reserved) Port Arbitration Table
0x240:0x27C Port VC1 arbitration table (Reserved) Port Arbitration Table
0x280:0x2BC Port VC2 arbitration table (Reserved) Port Arbitration Table
0x2C0:0x2FC Port VC3 arbitration table (Reserved) Port Arbitration Table
0x300:0x33C Port VC4 arbitration table (Reserved) Port Arbitration Table
0x340:0x37C Port VC5 arbitration table (Reserved) Port Arbitration Table
0x380:0x3BC Port VC6 arbitration table (Reserved) Port Arbitration Table
0x3C0:0x3FC Port VC7 arbitration table (Reserved) Port Arbitration Table
0x400:0x7FC Reserved PCIe spec corresponding section name
0x800:0x834 Advanced Error Reporting AER (optional) Advanced Error Reporting Capability
0x838:0xFFF Reserved
Table 6-2. PCI Type 0 Configuration Space Header (Endpoints), Rev2 Spec: Type 0 Configuration Space Header
0x000 Device ID Vendor ID Type 0 Configuration Space Header
0x004 Status Command Type 0 Configuration Space Header
0x008 Class Code Revision ID Type 0 Configuration Space Header
0x00C 0x00 Header Type 0x00 Cache Line Size Type 0 Configuration Space Header
0x010 Base Address 0 Base Address Registers (Offset 10h - 24h)
0x014 Base Address 1 Base Address Registers (Offset 10h - 24h)
0x018 Base Address 2 Base Address Registers (Offset 10h - 24h)
0x01C Base Address 3 Base Address Registers (Offset 10h - 24h)
0x020 Base Address 4 Base Address Registers (Offset 10h - 24h)
0x024 Base Address 5 Base Address Registers (Offset 10h - 24h)
0x028 Reserved Type 0 Configuration Space Header
0x02C Subsystem Device ID Subsystem Vendor ID Type 0 Configuration Space Header
0x030 Expansion ROM base address Type 0 Configuration Space Header
0x034 Reserved Capabilities PTR Type 0 Configuration Space Header
0x038 Reserved Type 0 Configuration Space Header
0x03C 0x00 0x00 Interrupt Pin Interrupt Line Type 0 Configuration Space Header
Table 6-3. PCI Type 1 Configuration Space Header (Root Ports) , Rev2 Spec: Type 1 Configuration Space Header
0x000 Device ID Vendor ID Type 1 Configuration Space Header
0x004 Status Command Type 1 Configuration Space Header
0x008 Class Code Revision ID Type 1 Configuration Space Header
0x00C
BIST Header Type Primary Latency Timer Cache
Line Size
Type 1 Configuration Space Header
Table 6–23. Correspondence Configuration Space Registers and PCIe Base Specification Rev. 2.0 Description (Part 2
of 5)
Byte Address Config Reg Offset 31:24 23:16 15:8 7:0 Corresponding Section in PCIe Specification