Altera IP Compiler for PCI Express - Manual (Page 33)

Chapter 2: Getting Started 2–17
Constraining the Design
August 2014 Altera Corporation IP Compiler for PCI Express User Guide
Example 2–2 illustrates the Synopsys timing constraints.
Specifying Device and Pin Assignments
If you want to download the design to a board, you must specify the device and pin
assignments for the chaining DMA example design. To make device and pin
assignments, follow these steps:
1. To select the device, on the Assignments menu, click Device.
2. In the Family list, select Stratix IV (GT/GX/E).
3. Scroll through the Available devices to select EP4SGX230KF40C2.
4. To add pin assignments for the EP4SGX230KF40C2 device, copy all the text
included in to the chaining DMA design example .qsf file,
<working_dir>\top_examples\chaining_dma\top_example_chaining_top.qsf to
your project .qsf file.
Example 2–2. Synopsys Timing Constraints
derive_pll_clocks
derive_clock_uncertainty
create_clock -period "100 MHz" -name {refclk} {refclk}
set_clock_groups -exclusive -group [get_clocks { refclk*clkout }] -group [get_clocks {
*div0*coreclkout}]
set_clock_groups -exclusive -group [get_clocks { *central_clk_div0* }] -group
[get_clocks { *_hssi_pcie_hip* }] -group [get_clocks { *central_clk_div1* }]
<The following 4 additional constraints are for Stratix IV ES Silicon only>
set_multicycle_path -from [get_registers *delay_reg*] -to [get_registers *all_one*] -
hold -start 1
set_multicycle_path -from [get_registers *delay_reg*] -to [get_registers *all_one*] -
setup -start 2
set_multicycle_path -from [get_registers *align*chk_cnt*] -to [get_registers
*align*chk_cnt*] -hold -start 1
set_multicycle_path -from [get_registers *align*chk_cnt*] -to [get_registers
*align*chk_cnt*] -setup -start 2