Altera IP Compiler for PCI Express - Manual (Page 134)

5–48 Chapter 5: IP Core Interfaces
Avalon-MM Application Interface
IP Compiler for PCI Express User Guide August 2014 Altera Corporation
f The IP Compiler for PCI Express variations with Avalon-MM interface implement the
Avalon-MM protocol described in the
Avalon Interface Specifications. Refer to this
specification for information about the Avalon-MM protocol, including timing
diagrams.
32-Bit Non-Bursting Avalon-MM CRA Slave Signals
This optional port for the full-featured IP core allows upstream PCI Express devices
and external Avalon-MM masters to access internal control and status registers.
Table 5–23 describes the CRA slave ports.
Clock v v “Clock Signals” on page 5–51
Reset and Status v v “Reset and Status Signals” on page 5–51
Physical and Test
Transceiver Control v v “Transceiver Control Signals” on page 5–53
Serial v v “Serial Interface Signals” on page 5–55
Pipe v v “PIPE Interface Signals” on page 5–56
Test v v “Test Signals” on page 5–58
Table 5–22. Avalon-MM Signal Groups in the IP Compiler with PCI Express Variations with an Avalon-MM
Interface (Part 2 of 2)
Signal Group
Full
Featured
Completer
Only
Description
Table 5–23. Avalon-MM CRA Slave Interface Signals
Signal Name in
Qsys
I/O Type Description
CraIrq_o/CraIrq_irq O Irq Interrupt request. A port request for an Avalon-MM interrupt.
CraReadData_o[31:0]/
Cra_readdata[31:0]
O Readdata Read data lines
CraWaitRequest_o/
Cra_waitrequest
O Waitrequest Wait request to hold off more requests
CraAddress_i[11:0]/
Cra_address[11:0]
I Address
An address space of 16,384 bytes is allocated for the control registers.
Avalon-MM slave addresses provide address resolution down to the
width of the slave data bus. Because all addresses are byte addresses,
this address logically goes down to bit 2. Bits 1 and 0 are 0.
CraByteEnable_i[3:0]/
Cra_byteenable[3:0]
I Byteenable Byte enable
CraChipSelect_i/
Cra_chipselect
I Chipselect Chip select signal to this slave
CraRead_i/Cra_read I Read Read enable
CraWrite_i/Cra_write I Write Write request
CraWriteData_i[31:0]/
Cra_writedata[31:0]
I Writedata Write data