Altera IP Compiler for PCI Express - Manual (Page 243)

Chapter 15: Testbench and Design Example 15–11
Chaining DMA Design Example
August 2014 Altera Corporation IP Compiler for PCI Express User Guide
The following modules are provided in both Verilog HDL and VHDL, and reflect each
hierarchical level:
■ altpcierd_example_app_chaining —This top level module contains the logic
related to the Avalon-ST interfaces as well as the logic related to the sideband
bus. This module is fully register bounded and can be used as an incremental
re-compile partition in the Quartus II compilation flow.
■ altpcierd_cdma_ast_rx , altpcierd_cdma_ast_rx_64,
altpcierd_cdma_ast_rx_128 —These modules implement the Avalon-ST receive
port for the chaining DMA. The Avalon-ST receive port converts the Avalon-ST
interface of the IP core to the descriptor/data interface used by the chaining
DMA submodules. altpcierd_cdma_ast_rx is used with the descriptor/data IP
core (through the ICM). altpcierd_cdma_ast_rx_64 is used with the 64-bit
Avalon-ST IP core. altpcierd_cdma_ast_rx_128 is used with the 128-bit Avalon-
ST IP core.
■ altpcierd_cdma_ast_tx , altpcierd_cdma_ast_tx_64,
altpcierd_cdma_ast_tx_128 —These modules implement the Avalon-ST
transmit port for the chaining DMA. The Avalon-ST transmit port converts the
descriptor/data interface of the chaining DMA submodules to the Avalon-ST
interface of the IP core. altpcierd_cdma_ast_tx is used with the descriptor/data
IP core (through the ICM). altpcierd_cdma_ast_tx_64 is used with the 64-bit
Avalon-ST IP core. altpcierd_cdma_ast_tx_128 is used with the 128-bit Avalon-
ST IP core.
■ altpcierd_cdma_ast_msi —This module converts MSI requests from the
chaining DMA submodules into Avalon-ST streaming data. This module is
only used with the descriptor/data IP core (through the ICM).
■ alpcierd_cdma_app_icm —This module arbitrates PCI Express packets for the
modules altpcierd_dma_dt (read or write) and altpcierd_rc_slave.
alpcierd_cdma_app_icm
instantiates the endpoint memory used for the DMA
read and write transfer.
■ altpcierd_compliance_test.v —This module provides the logic to perform CBB
via a push button.
■ altpcierd_rc_slave —This module provides the completer function for all
downstream accesses. It instantiates the altpcierd_rxtx_downstream_intf and
altpcierd_reg_access
modules. Downstream requests include programming of
chaining DMA control registers, reading of DMA status registers, and direct
read and write access to the endpoint target memory, bypassing the DMA.
■ altpcierd_rx_tx_downstream_intf —This module processes all downstream
read and write requests and handles transmission of completions. Requests
addressed to BARs 0, 1, 4, and 5 access the chaining DMA target memory
space. Requests addressed to BARs 2 and 3 access the chaining DMA control
and status register space using the altpcierd_reg_access module.
■ altpcierd_reg_access —This module provides access to all of the chaining DMA
control and status registers (BAR 2 and 3 address space). It provides address
decoding for all requests and multiplexing for completion data. All registers
are 32-bits wide. Control and status registers include the control registers in the
altpcierd_dma_prog_reg
module, status registers in the
altpcierd_read_dma_requester and altpcierd_write_dma_requester modules,