Altera IP Compiler for PCI Express - Manual (Page 309)

August 2014 Altera Corporation IP Compiler for PCI Express User Guide
17. Debugging
As you bring up your PCI Express system, you may face a number of issues related to
FPGA configuration, link training, BIOS enumeration, data transfer, and so on. This
chapter suggests some strategies to resolve the common issues that occur during
hardware bring-up.
Hardware Bring-Up Issues
Typically, PCI Express hardware bring-up involves the following steps:
1. System reset
2. Linking training
3. BIOS enumeration
The following sections, describe how to debug the hardware bring-up flow. Altera
recommends a systematic approach to diagnosing bring-up issues as illustrated in
Figure 17–1 .
Link Training
The physical layer automatically performs link training and initialization without
software intervention. This is a well-defined process to configure and initialize the
device's physical layer and link so that PCIe packets can be transmitted. If you
encounter link training issues, viewing the actual data in hardware should help you
determine the root cause. You can use the following tools to provide hardware
visibility:
■ Altera SignalTap ® II Embedded Logic Analyzer
■ Third-party PCIe analyzer
Debugging Link Training Issues Using Quartus II SignalTap II Logic Analyzer
You can use the SignalTap II Embedded Logic Analyzer to diagnose the LTSSM state
transitions that are occurring at the PIPE interface.
Figure 17–1. Debugging Link Training Issues
No
system reset
Does Link
Train
Correctly?
Check PIPE
Interface
Use PCIe
Analyzer
Soft Reset System to
Force Enumeration
Check Configuration
Space
Check LTSSM
Status
Yes Yes
No
Successful
OS/BIOS
Enumeration?
August 2014
<edit Part Number variable in chapter>