Altera IP Compiler for PCI Express - Manual (Page 49)

Chapter 3: Parameter Settings 3–13
IP Core Parameters
August 2014 Altera Corporation IP Compiler for PCI Express User Guide
Capabilities Parameters
The Capabilities page contains the parameters setting various capability properties of
the IP core. These parameters are described in
Table 3–11 . Some of these parameters
are stored in the Common Configuration Space Header . The byte offset within the
Common Configuration Space Header indicates the parameter address.
The IP Compiler for PCI Express parameter editor that appears in the Qsys flow
provides only the Link port number, Implement advance error reporting,
Implement ECRC check
, and Implement ECRC generation capabilities parameters.
For more information, refer to “Parameters in the Qsys Design Flow” on page 3–1 .
Prefetchable memory
(5)
Disable
32-bit I/O addressing
64-bit I/O addressing
Specifies what address widths are supported for the prefetchable
memory base
register and prefetchable memory limit register.
Notes to Table 3–10 :
(1) A prefetchable 64-bit BAR is supported. A non-prefetchable 64-bit BAR is not supported because in a typical system, the root port configuration
register of type 1 sets the maximum non-prefetchable memory window to 32-bits.
(2) The Qsys design flows do not support I/O space for BAR type mapping. I/O space is only supported for legacy endpoint port types.
(3) Only available for EP designs which require the use of the Header type 0 PCI configuration register.
(4) The Qsys design flows do not support the expansion ROM.
(5) Only available for RP designs which require the use of the Header type 1 PCI configuration register. Therefore, this option is not available in the
Qsys design flows.
Table 3–10. PCI Registers (Part 3 of 3)
Table 3–11. Capabilities Parameters (Part 1 of 4)
Parameter Value Description
Device Capabilities
0x084
Tags supported 4–256
Indicates the number of tags supported for non-posted requests transmitted by the
application layer. The following options are available:
Hard IP: 32 or 64 tags for ×1, ×4, and ×8
Soft IP: 4–256 tags for ×1 and ×4; 4–32 for ×8
Qsys design flows: 16 tags
This parameter sets the values in the Device Control register (0x088) of the PCI
Express capability structure described in
Table 6–7 on page 6–4 .
The transaction layer tracks all outstanding completions for non-posted requests
made by the application. This parameter configures the transaction layer for the
maximum number to track. The application layer must set the tag values in all
non-posted PCI Express headers to be less than this value. Values greater than 32
also set the extended tag field supported bit in the configuration space device
capabilities register. The application can only use tag numbers greater than 31 if
configuration software sets the extended tag field enable bit of the device control
register. This bit is available to the application as cfg_devcsr[8].
Implement
completion timeout
disable
0x0A8
On/Off
This option is only selectable for PCI Express version 2.0 and higher root ports . For
PCI Express version 2.0 and higher endpoints this option is forced to On. For PCI
Express version 1.0a and 1.1 variations, this option is forced to Off. The timeout
range is selectable. When On, the core supports the completion timeout disable
mechanism via the PCI Express Device Control Register 2. The application layer logic
must implement the actual completion timeout mechanism for the required ranges.