Transmit virtual channel arbitration, Configuration space – Altera IP Compiler for PCI Express User Manual
Page 69
Chapter 4: IP Core Architecture
4–11
Transaction Layer
August 2014
Altera Corporation
IP Compiler for PCI Express User Guide
Tracing a transaction through the transmit datapath involves the following steps:
1. The IP core informs the application layer that sufficient flow control credits exist
for a particular type of transaction. The IP core uses tx_cred[21:0] for the soft IP
implementation and tx_cred[35:0] for the hard IP implementation. The
application layer may choose to ignore this information.
2. The application layer requests a transaction layer packet transmission. The
application layer must provide the PCI Express transaction and must be prepared
to provide the entire data payload in consecutive cycles.
3. The IP core verifies that sufficient flow control credits exist, and acknowledges or
postpones the request.
4. The application layer forwards the transaction layer packet. The transaction layer
arbitrates among virtual channels, and then forwards the priority transaction layer
packet to the data link layer.
Transmit Virtual Channel Arbitration
For Stratix IV GX devices, the IP Compiler for PCI Express allows you to specify a
high and low priority virtual channel as specified in Chapter 6 of the
1.1
, or
2.0
. You can use the settings on the Buffer Setup page,
accessible from the Parameter Settings tab, to specify the number of virtual channels.
Refer to
“Buffer Setup Parameters” on page 3–16
.
Configuration Space
The configuration space implements the following configuration registers and
associated functions:
■
Header Type 0 Configuration Space for Endpoints
■
Header Type 1 Configuration Space for Root Ports
■
PCI Power Management Capability Structure
■
Message Signaled Interrupt (MSI) Capability Structure
■
Message Signaled Interrupt–X (MSI–X) Capability Structure
■
PCI Express Capability Structure
■
Virtual Channel Capabilities
The configuration space also generates all messages (PME#, INT, error, slot power
limit), MSI requests, and completion packets from configuration requests that flow in
the direction of the root complex, except slot power limit messages, which are
generated by a downstream port in the direction of the PCI Express link. All such
transactions are dependent upon the content of the PCI Express configuration space
as described in the
,
1.1
, or
2.0
.
f
Refer To
“Configuration Space Register Content” on page 6–1
,
1.1
, or
2.0
for the complete content of these registers.