Altera IP Compiler for PCI Express User Manual
Page 257
Chapter 15: Testbench and Design Example
15–25
Root Port Design Example
August 2014
Altera Corporation
IP Compiler for PCI Express User Guide
■
altpcierd_tl_cfg_sample.v
—accesses configuration space signals from the variant.
“Chaining DMA Design Example” on page 15–6
for a description of
this module.
Files in subdirectory <variation_name>_example/common/testbench:
■
altpcietb_bfm_ep_example_chaining_pipen1b.vo
—the simulation model for the
chaining DMA endpoint.
■
altpcietb_bfm_shmem.v
, altpcietb_bfm_shmem_common.v—root port memory
for a full description of this
module
■
altpcietb_bfm_rdwr.v—
requests PCI Express read and writes. Refer to the
for a full description of this module.
■
altpcietb_bfm_configure.v—
configures PCI Express configuration space
registers in the root port and endpoint. Refer to the
for a full description of this module
■
altpcietb_bfm_log.v,
and altpcietb_bfm_log_common.v—displays and logs
simulation messages. Refer to the
for a full
description of this module.
■
altpcietb_bfm_req_intf.v
, and altpcietb_bfm_req_intf_common.v—includes
tasks used to manage requests from altpcietb_bfm_rdwr to altpcietb_vc_intf_ast.
Refer to the
for a full description of this module.
■
altpcietb_bfm_constants.v—
contains global constants used by the root port BFM.
■
altpcietb_ltssm_mon.v
—displays LTSSM state transitions.
■
altpcietb_pipe_phy.v
, altpcietb_pipe_xtx2yrx.v, and altpcie_phasefifo.v—used to
simulate the PHY and support circuitry.
■
altpcie_pll_100_125.v
, altpcie_pll_100_250.v, altpcie_pll_125_250.v,
altpcie_pll_phy0.v
, altpcie_pll_phy1_62p5.v, altpcie_pll_phy2.v,
altpcie_pll_phy3_62p5.v
, altpcie_pll_phy4_62p5.v, altpcie_pll_phy5_62p5.v—
PLLs used for simulation. The type of PHY interface selected for the variant
determines which PLL is used.
■
altpcie_4sgx_alt_reconfig.v—
transceiver reconfiguration module used for
simulation.
■
altpcietb_rst_clk.v—
generates PCI Express and reference clock.